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31. 发明授权

US07839167B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US07839167B2
公开(公告)日：2010-11-23
申请号：US12356317
申请日：2009-01-20
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

32. 发明申请

US20050218930A1 Interconnection resources for programmable logic integrated circuit devices 有权
公开(公告)号：US20050218930A1
公开(公告)日：2005-10-06
申请号：US11087377
申请日：2005-03-22
申请人： James Schleicher , Jim Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , Jim Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： G06F7/50 , G06F7/506 , H03K19/173 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

33. 发明授权

US06614261B2 Interconnection and input/output resources for programable logic integrated circuit devices 有权
公开(公告)号：US06614261B2
公开(公告)日：2003-09-02
申请号：US10047618
申请日：2002-01-14
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K19177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

34. 发明授权

US06486702B1 Embedded memory blocks for programmable logic 有权
标题翻译：用于可编程逻辑的嵌入式存储块
公开(公告)号：US06486702B1
公开(公告)日：2002-11-26
申请号：US09609102
申请日：2000-06-30
申请人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
发明人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
IPC分类号： H03K19177
CPC分类号： G11C5/025 , H03K19/17736 , H03K19/1776
摘要： A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.
摘要翻译：高性能可编程逻辑架构具有嵌入式存储器（608）。布置在集成电路的周边或边缘。这通过缩短可编程互连（748）的长度来增强可编程逻辑集成电路的性能。在一个具体实施例中，存储块（703）沿着集成电路的顶部和底部边缘被排列成行。逻辑元件（805）可以直接编程路由并连接到相邻行和列中的逻辑块的驱动器块（809）。这允许信号的快速互连，而不使用全局可编程互连资源（815,825）。使用类似的直接可编程互连（828,88,835），逻辑块可以直接可编程地连接到存储器块而不使用全局可编程互连资源。本发明还提供了将多个存储器灵活组合或拼接在一起以形成所需尺寸的存储器的技术。

35. 发明授权

US06400635B1 Memory circuitry for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的存储电路
公开(公告)号：US06400635B1
公开(公告)日：2002-06-04
申请号：US09703914
申请日：2000-11-01
申请人： Tony Ngai , Nitin Prasad , Thungoc Tran
发明人： Tony Ngai , Nitin Prasad , Thungoc Tran
IPC分类号： G11C800
CPC分类号： H03K19/1776 , G11C7/1075 , G11C8/16 , G11C11/005
摘要： A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.
摘要翻译：可编程逻辑器件除了通常的可编程逻辑区域和可编程互连之外还包括具有多个可独立使用的写入和/或读出端口（例如，两个写入端口和两个读取端口）的至少一个存储器区域。存储器区域中的每个存储单元都可以从任何这些端口访问。这使得存储器区域能够用于提供一个相对较大的存储器或两个稍小的存储器，每个存储器占据完整存储器的一小部分。在后一种情况下，提供的两个存储器可以具有相对于彼此的许多不同尺寸的任何一个。操作存储器区域或存储器区域的部分的模式的许多不同模式或组合是可能的。

36. 发明授权

US06342792B1 Logic module circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的逻辑模块电路
公开(公告)号：US06342792B1
公开(公告)日：2002-01-29
申请号：US09518009
申请日：2000-03-02
申请人： Wei-Jen Huang , Sergey Shumarayev , Tony Ngai , Bruce Pedersen
发明人： Wei-Jen Huang , Sergey Shumarayev , Tony Ngai , Bruce Pedersen
IPC分类号： G06F738
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has logic modules with some inputs that are optimized for speed (to enhance the speed-performance of the logic modules). For example, some of the inputs may be programmably swappable within a logic module so that a speed-critical input signal can be more easily routed to a faster part of the logic module circuitry. Alternatively or in addition, drivers may be added to the logic module circuitry to improve the speed performance of some of the inputs to the logic module. The logic module may be provided with enhanced “lonely register” circuitry which allows the lonely register output signal to be fed back for use as an input to the combinatorial logic of the logic module. The registers in multiple logic modules may be directly chained to one another in a series.
摘要翻译：可编程逻辑集成电路器件具有逻辑模块，其具有针对速度优化的一些输入（以增强逻辑模块的速度性能）。例如，一些输入可以在逻辑模块内可编程地交换，使得速度至关重要的输入信号可以更容易地路由到逻辑模块电路的较快部分。或者或另外，可以将驱动器添加到逻辑模块电路中以提高逻辑模块的一些输入的速度性能。逻辑模块可以设置有增强的“孤独寄存器”电路，其允许将孤独寄存器输出信号反馈以用作逻辑模块的组合逻辑的输入。多个逻辑模块中的寄存器可以直接链接到一个系列中。

37. 发明授权

US06281704B1 High-performance interconnect 有权
公开(公告)号：US06281704B1
公开(公告)日：2001-08-28
申请号：US09810116
申请日：2001-03-15
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

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