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31. 发明申请

US20060274574A1 Phase-change memory device and method of writing a phase-change memory device 有权
公开(公告)号：US20060274574A1
公开(公告)日：2006-12-07
申请号：US11502563
申请日：2006-08-11
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C2013/0078 , G11C2013/0092
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

32. 发明申请

US20080106922A1 SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF WORD LINE CONTACTS 审中-公开
标题翻译：半导体存储器件和字线接线的布局结构
公开(公告)号：US20080106922A1
公开(公告)日：2008-05-08
申请号：US11735635
申请日：2007-04-16
申请人： Joon-Min Park , Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho
发明人： Joon-Min Park , Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C5/06 , G11C11/00
CPC分类号： G11C11/16 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/76
摘要： A semiconductor memory device and a layout structure of word line contacts, in which the semiconductor memory device includes an active region, a plurality of memory cells, and word line contacts. The active region is disposed in a first direction as a length direction on a semiconductor substrate and is used as a word line. The plurality of memory cells are disposed in the first direction on the active region and are each constructed of one variable resistance device and one diode device. In the word line contacts, at least one each is disposed between respective units, wherein each unit is constructed of predetermined numbers of memory cells on the active region. A bridge effect, such as a short-circuit between adjacent word lines, can be prevented or substantially reduced.
摘要翻译：半导体存储器件和字线触点的布局结构，其中半导体存储器件包括有源区，多个存储单元和字线触点。有源区域沿着半导体衬底上的长度方向的第一方向设置，并用作字线。多个存储单元在有源区域上沿第一方向设置，并且分别由一个可变电阻器件和一个二极管器件构成。在字线触点中，每个单元之间至少设置一个，其中每个单元由有源区上的预定数量的存储单元构成。可以防止或显着减少诸如相邻字线之间的短路的桥接效应。

33. 发明申请

US20070189104A1 Memory device with reduced word line resistance 有权
标题翻译：具有减少字线电阻的存储器件
公开(公告)号：US20070189104A1
公开(公告)日：2007-08-16
申请号：US11787931
申请日：2007-04-18
申请人： Beak-Hyung Cho , Du-Eung Kim
发明人： Beak-Hyung Cho , Du-Eung Kim
IPC分类号： G11C8/00
CPC分类号： G11C13/0028 , G11C8/08 , G11C8/14 , G11C13/0004
摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.
摘要翻译：存储器件包括多个块，每个块具有相应的存储器单元阵列和相应的本地字线。存储器件还包括耦合在每个本地字线和公共电压节点之间的相应开关器件。全局字线驱动器控制相应的开关装置对跨越包括访问的存储器单元的块的行中的相应本地字线导通。因此，公共电压节点处于被访问的存储器单元的当前路径中，具有最小的布局面积和当前路径的电阻。

34. 发明授权

US07215592B2 Memory device with reduced word line resistance 有权
公开(公告)号：US07215592B2
公开(公告)日：2007-05-08
申请号：US11035205
申请日：2005-01-12
申请人： Beak-Hyung Cho , Du-Eung Kim
发明人： Beak-Hyung Cho , Du-Eung Kim
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C13/0028 , G11C8/08 , G11C8/14 , G11C13/0004
摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

35. 发明申请

US20050195633A1 Method for programming phase-change memory array to set state and circuit of a phase-change memory device 有权
标题翻译：用于编程相变存储器阵列以设置相变存储器件的状态和电路的方法
公开(公告)号：US20050195633A1
公开(公告)日：2005-09-08
申请号：US11070196
申请日：2005-03-03
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
IPC分类号： G11C13/02 , G11C13/00 , G11C16/02 , G11C16/10 , G11C19/08 , H01L27/10 , H01L27/105 , H01L27/115
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.
摘要翻译：一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

36. 发明授权

US07502251B2 Phase-change memory device and method of writing a phase-change memory device 有权
标题翻译：相变存储器件以及相变存储器件的写入方法
公开(公告)号：US07502251B2
公开(公告)日：2009-03-10
申请号：US11502563
申请日：2006-08-11
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C2013/0078 , G11C2013/0092
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.
摘要翻译：相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程电路进入结晶状态。写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变至少一个复位和设置的脉冲电流的脉冲宽度和脉冲计数中的至少一个。

37. 发明授权

US07414915B2 Memory device with reduced word line resistance 有权
标题翻译：具有减少字线电阻的存储器件
公开(公告)号：US07414915B2
公开(公告)日：2008-08-19
申请号：US11787931
申请日：2007-04-18
申请人： Beak-Hyung Cho , Du-Eung Kim
发明人： Beak-Hyung Cho , Du-Eung Kim
IPC分类号： G11C8/00
CPC分类号： G11C13/0028 , G11C8/08 , G11C8/14 , G11C13/0004
摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.
摘要翻译：存储器件包括多个块，每个块具有相应的存储器单元阵列和相应的本地字线。存储器件还包括耦合在每个本地字线和公共电压节点之间的相应开关器件。全局字线驱动器控制相应的开关装置对跨越包括访问的存储器单元的块的行中的相应本地字线导通。因此，公共电压节点处于被访问的存储器单元的当前路径中，具有最小的布局面积和当前路径的电阻。

38. 发明授权

US07274586B2 Method for programming phase-change memory array to set state and circuit of a phase-change memory device 有权
标题翻译：用于编程相变存储器阵列以设置相变存储器件的状态和电路的方法
公开(公告)号：US07274586B2
公开(公告)日：2007-09-25
申请号：US11070196
申请日：2005-03-03
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.
摘要翻译：一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

39. 发明申请

US20050270883A1 Memory device with reduced word line resistance 有权
标题翻译：具有减少字线电阻的存储器件
公开(公告)号：US20050270883A1
公开(公告)日：2005-12-08
申请号：US11035205
申请日：2005-01-12
申请人： Beak-Hyung Cho , Du-Eung Kim
发明人： Beak-Hyung Cho , Du-Eung Kim
IPC分类号： G11C13/00 , G11C8/00 , G11C8/08 , G11C8/14 , G11C13/02
CPC分类号： G11C13/0028 , G11C8/08 , G11C8/14 , G11C13/0004
摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.
摘要翻译：存储器件包括多个块，每个块具有相应的存储器单元阵列和相应的本地字线。存储器件还包括耦合在每个本地字线和公共电压节点之间的相应开关器件。全局字线驱动器控制相应的开关装置对跨越包括访问的存储器单元的块的行中的相应本地字线导通。因此，公共电压节点处于被访问的存储器单元的当前路径中，具有最小的布局面积和当前路径的电阻。

40. 发明申请

US20050169093A1 Phase-change memory device and method of writing a phase-change memory device 有权
标题翻译：相变存储器件以及相变存储器件的写入方法
公开(公告)号：US20050169093A1
公开(公告)日：2005-08-04
申请号：US10919371
申请日：2004-08-17
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C13/02 , G11C8/00 , G11C16/02
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.
摘要翻译：相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程电路进入结晶状态。写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变复位和设置脉冲电流中的至少一个的脉冲宽度和脉冲计数中的至少一个。

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