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    • 32. 发明授权
    • Slide type mobile phone holder
    • US11424782B2
    • 2022-08-23
    • US17220243
    • 2021-04-01
    • Chien-Ting Lin
    • Chien-Ting Lin
    • F16M11/04H04B1/3877H04M1/04
    • A slide type mobile phone holder includes: a first coupling portion having a first clamp portion and provided with first coupling and outer accommodation portions at first coupling and outer surfaces thereof, respectively, a first coupling wall and a first sliding groove provided between the first coupling and outer accommodation portions, the first coupling accommodation portion having a first coupling protrusion and a first hook; a second coupling portion having a second clamp portion and provided with second coupling and outer accommodation portions at second coupling and outer surfaces thereof, respectively, a second coupling wall and a second sliding groove provided between the second coupling and outer accommodation portions, the second coupling accommodation portion having a second coupling protrusion and a second hook; and a spring member abutting against the first and second coupling protrusions. The first and second coupling portions are assembled together for clamping a mobile phone.
    • 38. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    • 半导体器件及其制造方法
    • US20130126972A1
    • 2013-05-23
    • US13304086
    • 2011-11-23
    • Chang-Tzu WangMei-Ling ChaoChien-Ting Lin
    • Chang-Tzu WangMei-Ling ChaoChien-Ting Lin
    • H01L27/12H01L21/336
    • H01L29/66795H01L21/26513H01L21/823821H01L27/0924
    • A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.
    • 提供了一种半导体器件及其制造方法。 半导体器件包括具有第二导电类型的第一导电类型,鳍状物,栅极,源极和漏极区域以及第二导电类型的第一掺杂区域的衬底。 在基板上形成多个隔离结构。 翅片设置在两个相邻隔离结构之间的基板上。 栅极设置在隔离结构上并覆盖翅片的一部分,其中由栅极覆盖的鳍的部分是第一导电类型。 源极和漏极区域在栅极的相应侧配置在鳍片中。 第一掺杂区域配置在源极和漏极区域下方的鳍片中,并与衬底相邻。 第一掺杂区的杂质浓度低于源区和漏区。
    • 39. 发明授权
    • Method for fabricating a metal gate structure
    • 金属栅极结构的制造方法
    • US08198151B2
    • 2012-06-12
    • US12890725
    • 2010-09-27
    • Chien-Ting LinChe-Hua HsuLi-Wei Cheng
    • Chien-Ting LinChe-Hua HsuLi-Wei Cheng
    • H01L21/8238
    • H01L21/28123H01L21/823437H01L21/823475H01L21/823481H01L29/495H01L29/4966H01L29/513H01L29/517H01L29/66545
    • A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.
    • 提供一种制造金属栅极结构的方法。 该方法包括:提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极,其中第一栅极位于有源区上,而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料,直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹槽; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。