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31. 发明授权

US5331220A Soft wakeup output buffer 失效
标题翻译：软唤醒输出缓冲区
公开(公告)号：US5331220A
公开(公告)日：1994-07-19
申请号：US016643
申请日：1993-02-12
申请人： Kerry M. Pierce , Charles R. Erickson
发明人： Kerry M. Pierce , Charles R. Erickson
IPC分类号： H03K19/173 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/092 , H03K19/00
CPC分类号： H03K19/00361
摘要： Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high slew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
摘要翻译：当集成电路器件的许多高电容端子同时从一个逻辑状态移动到另一个逻辑状态时，电源或接地电压可能会波动。特别是在输出缓冲器的全局高阻抗状态释放之后，其中输出信号被被动地驱动到选择的逻辑状态。为了防止电源和接地电压变化，缓冲器具有用于以慢响应（高转换）模式操作的装置。压摆率控制电路响应于高阻抗信号将缓冲器移动到慢响应模式。当转换速率控制电路接收到结束缓冲器的高阻状态的信号时，对该信号施加延迟，并且在延迟时间允许缓冲器移动到快速响应模式之后。当高电容端子移动到新的逻辑状态时，慢速缓冲器响应和缓慢的电压变化可以防止许多端子的同时切换响应电源或接地电压的波动。

32. 发明授权

US6100705A Method and structure for viewing static signal levels on integrated circuits using electron beam deflection device 有权
标题翻译：使用电子束偏转装置观察集成电路静态信号电平的方法和结构
公开(公告)号：US6100705A
公开(公告)日：2000-08-08
申请号：US216278
申请日：1998-12-18
申请人： Charles R. Erickson , Brian D. Erickson
发明人： Charles R. Erickson , Brian D. Erickson
IPC分类号： G01Q10/06 , G01Q30/02 , G01R31/307 , G01R31/305
CPC分类号： G01R31/307
摘要： A method and structure for testing static signal levels on an integrated circuit device using an electron beam deflection device. Each static signal is applied to a first terminal of a switch, such as an AND gate, an OR gate, or a pass transistor. An alternating control signal of approximately 1 MHz is transmitted to a second terminal of the switch such that the switch generates an output signal that is either constant (if the static signal is at a first level), or has a frequency equal to that of the alternating control signal (if the static signal is at a second level). The output signal is transmitted to a pad located on an exposed surface of the integrated circuit, where an electron beam deflection device is utilized to determine the static signal level by detecting the presence or absence of an alternating signal. A method for determining the voltage level of a signal includes applying the signal to the gate of a transistor and an alternating control signal to an input terminal. An electron beam deflection device is then utilized to measure the voltage level of a signal generated at an output terminal of the transistor. The voltage level of the signal is then calculated by adding the measured voltage level and a threshold voltage of the transistor.
摘要翻译：一种使用电子束偏转装置在集成电路装置上测试静态信号电平的方法和结构。每个静态信号被施加到开关的第一端，诸如与门，或门或传输晶体管。大约1MHz的交替控制信号被发送到开关的第二端，使得开关产生一个恒定的输出信号（如果静态信号处于第一电平），或者具有等于交替控制信号（如果静态信号处于第二级）。输出信号被传送到位于集成电路的暴露表面上的焊盘，其中电子束偏转装置用于通过检测交流信号的存在或不存在来确定静态信号电平。用于确定信号的电压电平的方法包括将信号施加到晶体管的栅极和将交替的控制信号施加到输入端子。然后利用电子束偏转装置来测量在晶体管的输出端产生的信号的电压电平。然后通过将测量的电压电平和晶体管的阈值电压相加来计算信号的电压电平。

33. 发明授权

US5970142A Configuration stream encryption 失效
标题翻译：配置流加密
公开(公告)号：US5970142A
公开(公告)日：1999-10-19
申请号：US703117
申请日：1996-08-26
申请人： Charles R. Erickson
发明人： Charles R. Erickson
IPC分类号： G06F1/00 , G06F12/14 , G06F21/00 , H04L9/00
CPC分类号： G06F21/57 , G06F12/1408 , G06F21/85
摘要： A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
摘要翻译：在可编程逻辑器件（PLD）和存储器件之间传送加密配置数据的方法包括在本发明的一部分中。该方法包括以下步骤。将存储在存储设备中的加密配置数据发送到PLD。解密加密的配置数据以生成PLD中的配置数据的副本。使用配置数据的副本配置PLD。在一个实施例中，PLD将密钥发送到存储设备。在另一个实施例中，密钥分别输入到存储设备和PLD中，并且从未在PLD和存储设备之间传送密钥。在另一个实施例中，键仅输入到PLD中。密钥用于加密配置数据。

34. 发明授权

US5909453A Lookahead structure for fast scan testing 失效
标题翻译：前瞻性结构，用于快速扫描测试
公开(公告)号：US5909453A
公开(公告)日：1999-06-01
申请号：US887357
申请日：1997-07-02
申请人： Steven H. Kelem , Charles R. Erickson
发明人： Steven H. Kelem , Charles R. Erickson
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318558 , G01R31/318541
摘要： A scan lookahead skip structure that allows a programmable number of test bits, I/O blocks, flip-flops, or columns to be skipped. One embodiment of the structure includes multiplexers to skip the scan paths for several adjacent I/O blocks, flip-flops, or columns, thereby reducing the number of clock cycles and overall delay required to utilize the scan path.
摘要翻译：扫描前瞻跳转结构允许跳过可编程数量的测试位，I / O模块，触发器或列。该结构的一个实施例包括多路复用器以跳过几个相邻I / O块，触发器或列的扫描路径，由此减少利用扫描路径所需的时钟周期数和总体延迟。

35. 发明授权

US5844829A Configurable parallel and bit serial load apparatus 失效
公开(公告)号：US5844829A
公开(公告)日：1998-12-01
申请号：US985392
申请日：1997-12-04
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

36. 发明授权

US5838167A Method and structure for loading data into several IC devices 失效
标题翻译：将数据加载到多个IC设备中的方法和结构
公开(公告)号：US5838167A
公开(公告)日：1998-11-17
申请号：US855029
申请日：1997-05-13
申请人： Charles R. Erickson , Lawrence Cy-Wei Hung
发明人： Charles R. Erickson , Lawrence Cy-Wei Hung
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/177 , G06F17/5054 , H03K19/17704
摘要： An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.
摘要翻译：一种用于减少将配置数据加载到现场可编程门阵列（FPGA）或其他集成电路器件所需的时间量的装置和方法。在优选实施例中，串行排列的FPGA从公共数据总线接收连续的数据流。当第一个FPGA达到加载完成状态时，启用令牌从第一个FPGA传递到下一个FPGA的使能输入。该过程重复，直到所有设备完全加载或完全配置为止。

37. 发明授权

US5742531A Configurable parallel and bit serial load apparatus 失效
公开(公告)号：US5742531A
公开(公告)日：1998-04-21
申请号：US642758
申请日：1996-05-03
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

38. 发明授权

US5646564A Phase-locked delay loop for clock correction 失效
标题翻译：用于时钟校正的锁相延迟环
公开(公告)号：US5646564A
公开(公告)日：1997-07-08
申请号：US632523
申请日：1996-04-12
申请人： Charles R. Erickson , Philip M. Freidin , Kerry M. Pierce
发明人： Charles R. Erickson , Philip M. Freidin , Kerry M. Pierce
IPC分类号： G06F1/10 , H03K5/15 , H03L7/081 , H03L7/085 , H03L7/00 , H03K5/00
CPC分类号： H03L7/0812 , G06F1/10 , H03K5/1504 , H03L7/085
摘要： A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship. In one form of the invention, an inventer adapted to invert one of the reference input clock and output clock signals, and a divide by N circuit for lowering the clock frequency while roughly adjusting the delay.
摘要翻译：受控的延迟路径将选定的延迟插入到时钟分配电路中以产生等于相对于参考输入时钟信号的整数个时钟周期的总时钟延迟，或者产生与参考时钟信号的选择的相位关系。本发明的延迟路径校正在具有宽范围的可能的系统时钟频率或具有时钟信号的可编程路由以及因此具有宽范围的操作延迟的电路中特别有用。参考输入时钟信号通过接收参考输入时钟信号和反馈信号的相位检测器被引导到可选择的受电压控制的延迟元件的范围，并产生误差电压，该误差电压调节电压控制的延迟元件以产生输出时钟信号。可以包括额外的可选择的延迟，其创建偏移选项并允许选择引导，滞后或同相参考输入时钟/输出时钟关系。在本发明的一种形式中，适用于反转参考输入时钟和输出时钟信号之一的发明者，以及用于降低时钟频率的N电路的除法，同时大致调整延迟。

39. 发明授权

US5640106A Method and structure for loading data into several IC devices 失效
标题翻译：将数据加载到多个IC设备中的方法和结构
公开(公告)号：US5640106A
公开(公告)日：1997-06-17
申请号：US451781
申请日：1995-05-26
申请人： Charles R. Erickson , Lawrence Cy-Wei Hung
发明人： Charles R. Erickson , Lawrence Cy-Wei Hung
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/177 , G06F17/5054 , H03K19/17704
摘要： An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.
摘要翻译：一种用于减少将配置数据加载到现场可编程门阵列（FPGA）或其他集成电路器件所需的时间量的装置和方法。在优选实施例中，串行排列的FPGA从公共数据总线接收连续的数据流。当第一个FPGA达到加载完成状态时，启用令牌从第一个FPGA传递到下一个FPGA的使能输入。该过程重复，直到所有设备完全加载或完全配置为止。

40. 发明授权

US5631577A Synchronous dual port RAM 失效
标题翻译：同步双端口RAM
公开(公告)号：US5631577A
公开(公告)日：1997-05-20
申请号：US668276
申请日：1996-06-21
申请人： Philip M. Freidin , Edmond Y. Cheung , Charles R. Erickson , Tsung-Lu Syu
发明人： Philip M. Freidin , Edmond Y. Cheung , Charles R. Erickson , Tsung-Lu Syu
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/173 , H03K19/177 , G11C13/00
CPC分类号： H03K19/1736 , G11C7/1072 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/17704
摘要： A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.
摘要翻译：双端口模式下的可配置逻辑块（CLB）使用一个地址将相同的信息写入第一个RAM和第二个RAM。提供给第二函数发生器的输入信号可以用于独立于写入操作而非甚至异步地读取，从而显着地增加使用两组RAM的应用速度。同步模式下的CLB锁存适当的地址和数据信号，并产生选通的写使能信号。选通信号是自定时的，即写入操作是完全自动的，从而确保写操作在一个时钟周期内发生。

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