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31. 发明申请

US20050080970A1 Chipset support for managing hardware interrupts in a virtual machine system 有权
标题翻译：芯片组支持管理虚拟机系统中的硬件中断
公开(公告)号：US20050080970A1
公开(公告)日：2005-04-14
申请号：US10676890
申请日：2003-09-30
申请人： Stalinselvaraj Jeyasingh , Andrew Anderson , Steven Bennett , Erik Cota-Robles , Alain Kagi , Gilbert Neiger , Richard Uhlig
发明人： Stalinselvaraj Jeyasingh , Andrew Anderson , Steven Bennett , Erik Cota-Robles , Alain Kagi , Gilbert Neiger , Richard Uhlig
IPC分类号： G06F9/455 , G06F9/48 , G06F13/24
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/4812
摘要： In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.
摘要翻译：在一个实施例中，装置包括与中断控制器和多个中断请求线耦合的一组多路复用块以及耦合到该多路复用块集合的虚拟机监视块（VMM）。每个复用块对应于不同的中断请求行。每个多路复用块将根据该多路复用块的当前配置值将经由相应的中断请求线接收到的中断请求信号发送到中断控制器或VMM块。

32. 发明申请

US20050080937A1 Invalidating translation lookaside buffer entries in a virtual machine (VM) system 有权
标题翻译：使虚拟机（VM）系统中的翻译后备缓冲区条目无效
公开(公告)号：US20050080937A1
公开(公告)日：2005-04-14
申请号：US10973678
申请日：2004-10-25
申请人： Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael Kozuch , Gilbert Neiger , Richard Uhlig
发明人： Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael Kozuch , Gilbert Neiger , Richard Uhlig
IPC分类号： G06F12/10 , G06F3/00
CPC分类号： G06F12/1027 , G06F9/30076 , G06F12/1036 , G06F2212/151
摘要： One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.
摘要翻译：本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。处理器中的TLB具有多个TLB条目。当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

33. 发明申请

US20170090807A1 TECHNOLOGIES FOR MANAGING CONNECTED DATA ON PERSISTENT MEMORY-BASED SYSTEMS 审中-公开
公开(公告)号：US20170090807A1
公开(公告)日：2017-03-30
申请号：US14866941
申请日：2015-09-26
申请人： Vishakha Gupta , Alain Kagi , Philip Lantz , Subramanya Dulloor
发明人： Vishakha Gupta , Alain Kagi , Philip Lantz , Subramanya Dulloor
IPC分类号： G06F3/06
CPC分类号： G06F16/90 , G06F12/0871 , G06F12/0897 , G06F2212/163 , G06F2212/214 , G06F2212/466
摘要： Managing connected data, such as a graph data store, includes a computing device with persistent memory and volatile memory. The computing device stores a graph data store with a plurality of nodes and edges in persistent memory. Each of the edges defines the relationship between at least two of the nodes. The nodes and edges may contain tags and properties containing additional information. In response to a search request query, the computing device generates an iterator object stored in volatile memory with a reference to one or more nodes and/or edges in the graph data store. The split between volatile and persistent memory allocation could be used for other objects, such as allocators and transactions. Other embodiments are described and claimed.

34. 发明授权

US07225441B2 Mechanism for providing power management through virtualization 有权
标题翻译：通过虚拟化提供电源管理的机制
公开(公告)号：US07225441B2
公开(公告)日：2007-05-29
申请号：US09752586
申请日：2000-12-27
申请人： Michael Kozuch , Stephen Chou , Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Gilbert Neiger , Sebastian Schoenberg , Richard Uhlig
发明人： Michael Kozuch , Stephen Chou , Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Gilbert Neiger , Sebastian Schoenberg , Richard Uhlig
IPC分类号： G06F9/455 , G06F1/26 , G06F15/173
CPC分类号： G06F1/3203
摘要： In one embodiment, a method for providing power management via virtualization includes monitoring the utilization of a host platform device by one or more virtual machines and managing power consumption of the host platform device based on the results of monitoring.
摘要翻译：在一个实施例中，用于经由虚拟化提供电力管理的方法包括通过一个或多个虚拟机监视主机平台设备的利用率，并且基于监视的结果来管理主机平台设备的功耗。

35. 发明申请

US20060064697A1 Method and apparatus for scheduling virtual machine access to shared resources 有权
标题翻译：调度虚拟机访问共享资源的方法和装置
公开(公告)号：US20060064697A1
公开(公告)日：2006-03-23
申请号：US10947902
申请日：2004-09-23
申请人： Alain Kagi , Andrew Anderson , Steven Bennett , Erik Cota-Robles , Gregory Jablonski
发明人： Alain Kagi , Andrew Anderson , Steven Bennett , Erik Cota-Robles , Gregory Jablonski
IPC分类号： G06F9/46
CPC分类号： G06F9/5011
摘要： A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.
摘要翻译：用于管理来自虚拟机的IO请求以访问物理机器上的IO资源的方法包括确定与IO请求相关联的请求优先级。响应于确定请求优先级，IO请求被放置在适当的队列中。

36. 发明授权

US06907600B2 Virtual translation lookaside buffer 有权
公开(公告)号：US06907600B2
公开(公告)日：2005-06-14
申请号：US09752133
申请日：2000-12-27
申请人： Gilbert Neiger , Stephen Chou , Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael Kozuch , Richard Uhlig , Sebastian Schoenberg
发明人： Gilbert Neiger , Stephen Chou , Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael Kozuch , Richard Uhlig , Sebastian Schoenberg
IPC分类号： G06F9/455 , G06F12/10 , G06F12/14 , G06F9/45
CPC分类号： G06F9/45537 , G06F12/1036 , G06F12/1491
摘要： In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content of the active translation data structure to conform to the content of the guest translations data structure. The content of the active translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).

37. 发明申请

US20050060702A1 Optimizing processor-managed resources based on the behavior of a virtual machine monitor 有权
标题翻译：根据虚拟机监视器的行为优化处理器管理的资源
公开(公告)号：US20050060702A1
公开(公告)日：2005-03-17
申请号：US10663163
申请日：2003-09-15
申请人： Steven Bennett , Andrew Anderson , Stalinselvaraj Jeyasingh , Alain Kagi , Gilbert Neiger , Richard Uhlig , Xiang Zou , Lawrence Smith , Scott Rodgers
发明人： Steven Bennett , Andrew Anderson , Stalinselvaraj Jeyasingh , Alain Kagi , Gilbert Neiger , Richard Uhlig , Xiang Zou , Lawrence Smith , Scott Rodgers
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/45558 , G06F2009/45583
摘要： In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.
摘要翻译：在一个实施例中，识别相对于一个或多个虚拟机（VM）的虚拟机监视器（VMM）的预定义行为，并且基于所述一个或多个虚拟机（VM）的预定义行为来利用与所述一个或多个VM相关联的处理器管理的资源 VMM。

38. 发明授权

US06460124B1 Method of using delays to speed processing of inferred critical program portions 有权
标题翻译：使用延迟加速推断的关键程序部分的方法
公开(公告)号：US06460124B1
公开(公告)日：2002-10-01
申请号：US09693030
申请日：2000-10-20
申请人： Alain Kagi , James R. Goodman , Ravi Rajwar
发明人： Alain Kagi , James R. Goodman , Ravi Rajwar
IPC分类号： G06F1208
CPC分类号： G06F12/0806 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/528
摘要： Critical sections of a program, providing exclusive access to shared data in a multi-processor architecture may be inferred from standard instructions and used to invoke a cache protocol that delays the response of requests of other cache and thus counter intuitively improving performance of the system. During this delay, read-only copies of data may be provided and the delay may recognize two priorities of requests, one of which is not delayed so as to improve the release of locks held by different processors.
摘要翻译：可以从标准指令推断程序的关键部分，提供对多处理器架构中的共享数据的独占访问，并且用于调用延迟其他缓存的请求的响应的缓存协议，从而直观地改善系统的性能。在该延迟期间，可以提供数据的只读副本，并且延迟可以识别请求的两个优先级，其中一个优先级不被延迟，以便改善由不同处理器保持的锁的释放。

39. 发明授权

US08543772B2 Invalidating translation lookaside buffer entries in a virtual machine (VM) system 有权
标题翻译：使虚拟机（VM）系统中的翻译后备缓冲区条目无效
公开(公告)号：US08543772B2
公开(公告)日：2013-09-24
申请号：US12959109
申请日：2010-12-02
申请人： Eric C. Cota-Robles , Andy Glew , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
发明人： Eric C. Cota-Robles , Andy Glew , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F9/30076 , G06F12/1036 , G06F2212/151
摘要： One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.
摘要翻译：本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。处理器中的TLB具有多个TLB条目。当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

40. 发明授权

US07818808B1 Processor mode for limiting the operation of guest software running on a virtual machine supported by a virtual machine monitor 有权
标题翻译：处理器模式，用于限制在虚拟机监视器支持的虚拟机上运行的客户机软件的操作
公开(公告)号：US07818808B1
公开(公告)日：2010-10-19
申请号：US09752134
申请日：2000-12-27
申请人： Gilbert Neiger , Stephen Chou , Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael Kozuch , Richard Uhlig
发明人： Gilbert Neiger , Stephen Chou , Erik Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael Kozuch , Richard Uhlig
IPC分类号： G06F9/455 , G06F21/00
CPC分类号： G06F12/145 , G06F9/45558 , G06F2009/45583
摘要： In one embodiment, a processor mode is provided for guest software. The processor mode enables the guest software to operate at a privilege level intended by the guest software. When the guest software attempts to perform an operation restricted by the processor mode, the processor mode is exited to transfer control over the operation to a virtual-machine monitor, which runs outside this processor mode.
摘要翻译：在一个实施例中，为客户软件提供处理器模式。处理器模式使宾客软件能够以访客软件所规定的特权级别运行。当客户软件尝试执行受处理器模式限制的操作时，退出处理器模式以将操作的控制转移到在该处理器模式之外运行的虚拟机监视器。

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