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31. 发明授权

US5995417A Scheme for page erase and erase verify in a non-volatile memory array 有权
标题翻译：在非易失性存储器阵列中进行页擦除和擦除验证的方案
公开(公告)号：US5995417A
公开(公告)日：1999-11-30
申请号：US175646
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
发明人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
IPC分类号： G11C16/02 , G11C16/16 , G11C16/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.
摘要翻译：非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页被擦除和擦除验证。擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他连接到未选择用于页面擦除的字线的MOS晶体管。在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

32. 发明授权

US5926520A Shift register functioning in both latch mode and counter mode and flash memory employing same 失效
标题翻译：移位寄存器在锁存模式和计数器模式下工作，闪速存储器采用相同的方式
公开(公告)号：US5926520A
公开(公告)日：1999-07-20
申请号：US885174
申请日：1997-06-30
申请人： Masaru Yano
发明人： Masaru Yano
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C19/00 , H03K21/00
CPC分类号： G11C16/06
摘要： The shift register includes a front stage latch portion for inputting input data when a clock signal is at a first level and latching the input data when the clock signal is at a second level, a rear stage latch portion for inputting data from the front stage latch portion when the clock signal is at the second level and latching the input data when the clock signal is at the first level, an input switch for connecting a data input terminal to the front stage latch portion when a mode switching signal is at a first level, and a feedback switch for connecting the rear stage latch portion to the front stage latch portion when the mode switching signal is at a second level. A latch mode clock signal is provided as the aforementioned clock signal when the mode switching signal is at the first level, and a counter mode clock signal or front stage shift register latch output signal is provided as the aforementioned clock signal when the mode switching signal is at the second level. The shift register functions in latch mode when the mode switching signal is at the first level, and functions with a plurality of stages thereof as a counter when at the second level. A flash memory equipped with the above shift registers which have a function whereby command flags of decoded external command signals are latched, and a counter function whereby counting is performed with the plural shift register stages.
摘要翻译：移位寄存器包括前级锁存部分，用于当时钟信号处于第一电平时输入输入数据，并且当时钟信号处于第二电平时锁存输入数据;后级锁存部分，用于从前级锁存器输入数据当时钟信号处于第二电平并且当时钟信号处于第一电平时锁存输入数据;当模式切换信号处于第一电平时用于将数据输入端连接到前级锁存器部分的输入开关以及反馈开关，用于当模式切换信号处于第二电平时将后级锁存部分连接到前级锁存器部分。当模式切换信号处于第一电平时，提供锁存模式时钟信号作为上述时钟信号，并且当模式切换信号为模式切换信号时，提供计数器模式时钟信号或前级移位寄存器锁存输出信号作为上述时钟信号在第二级。当模式切换信号处于第一电平时，移位寄存器在锁存模式下起作用，并且当处于第二电平时，以多个级作为计数器起作用。具有上述移位寄存器的闪速存储器具有锁定解码的外部命令信号的指令标志的功能，以及用多个移位寄存器级进行计数的计数器功能。

33. 发明授权

US4849749A Electronic lock and key switch having key identifying function 失效
标题翻译：电子锁和钥匙开关具有钥匙识别功能
公开(公告)号：US4849749A
公开(公告)日：1989-07-18
申请号：US18589
申请日：1987-02-25
申请人： Masaaki Fukamachi , Nobuyuki Onitsuka , Masaru Yano , Kazuhiro Sakata
发明人： Masaaki Fukamachi , Nobuyuki Onitsuka , Masaru Yano , Kazuhiro Sakata
IPC分类号： G07C9/00
CPC分类号： G07C9/00738 , Y10T70/7079 , Y10T70/7904
摘要： When a key is inserted into a key hole of a lock, magnetism creating means creates a magnetic flux corresponding to a predetermined magnetic code set in the key. Magnetism detecting means detects the magnetic flux and outputs a signal representing the detected magnetic flux. Decision means compares the signal value with a predetermined value, and outputs an agreement signal when the two values are the same. Driving means enables at least unlocking by key operation in response to the agreement signal. The magnetism detecting means outputs, as the above signal, a voltage corresponding to the magnitude of the detected magnetic flux or pulses having a frequency corresponding to same. At least one of material, dimensions, and thickness of the magnetic element determines the predetermined magnetic code. Further, an unlocking mechanism has a magnetic actuator which unlocks the lock by coupling the lock with unlocking means via a cam in response to the agreement signal.
摘要翻译：当钥匙被插入到锁的钥匙孔中时，磁力产生装置产生对应于钥匙中设定的预定磁代码的磁通量。磁检测装置检测磁通并输出表示检测的磁通量的信号。决定装置将信号值与预定值进行比较，当两个值相同时，输出协议信号。驱动装置至少通过按照协议信号的键操作进行解锁。磁检测装置作为上述信号输出对应于检测到的磁通量的大小的电压或具有与其相对应的频率的脉冲。磁性元件的材料，尺寸和厚度中的至少一个确定预定的磁性代码。此外，解锁机构具有磁致动器，其通过响应于协议信号经由凸轮将锁与解锁装置相耦合来解锁锁。

34. 发明授权

US08717816B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08717816B2
公开(公告)日：2014-05-06
申请号：US13404710
申请日：2012-02-24
申请人： Masaru Yano
发明人： Masaru Yano
IPC分类号： G11C11/34
CPC分类号： G11C16/08 , G11C8/08 , G11C16/0483
摘要： A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.
摘要翻译：能够减少施加到存储器阵列上的字线并减小芯片面积的电场的闪速存储器100包括存储器阵列110，设置在存储器阵列的行方向的端部的字线解码器120，选择一个根据地址信号在存储器阵列中预定的存储块，并将选择信号输出到所选择的存储块;以及字线驱动电路130，其包括布置在存储器阵列110A和110B之间的开关电路，并切换工作的应用根据选择信号向存储单元施加电压，以及泵电路，提高选择信号的电压电平。字线解码器120具有发送选择信号的线WR（i）。线WR（i）连接到字线驱动电路130的开关电路。

35. 发明授权

US08693249B2 Semiconductor memory devices 有权
标题翻译：半导体存储器件
公开(公告)号：US08693249B2
公开(公告)日：2014-04-08
申请号：US13350338
申请日：2012-01-13
申请人： Masaru Yano , Lu-Ping Chiang
发明人： Masaru Yano , Lu-Ping Chiang
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C16/0483
摘要： A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.
摘要翻译：半导体存储器件包括存储器阵列，行选择电路和位线选择电路。存储器阵列由多个单元单元组成，其中每个单元单元具有串联连接的存储单元。行选择电路选择单元单元的行方向的存储单元，并且位线选择电路从耦合到单元单元的偶位线和奇数位线中选择位线。位线选择电路包括第一选择部分，其包括用于选择性地将偶数或奇数位线耦合到传感器电路的选择晶体管，以及包括偏置晶体管的第二选择部分，用于选择性地将偶数或奇数位线耦合到提供偏置的电压源，其中偏置晶体管和存储单元形成在公共井中。

36. 发明授权

US08325523B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08325523B2
公开(公告)日：2012-12-04
申请号：US13195722
申请日：2011-08-01
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明的实施例提供一种半导体器件，其包括：包括非易失性存储器单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明的一个实施例还提供了一种控制半导体器件的方法。

37. 发明申请

US20120084491A1 Flash Memory for Code and Data Storage 有权
标题翻译：用于代码和数据存储的闪存
公开(公告)号：US20120084491A1
公开(公告)日：2012-04-05
申请号：US13250077
申请日：2011-09-30
申请人： Eungjoon Park , Robin John Jigour , Jooweon Park , Masaru Yano
发明人： Eungjoon Park , Robin John Jigour , Jooweon Park , Masaru Yano
IPC分类号： G06F12/02
CPC分类号： G06F3/061 , G06F3/0608 , G06F3/0658 , G06F3/0688 , G06F12/0246 , G06F2212/7208 , G11C11/005 , G11C16/0416 , G11C16/0483 , G11C2216/30
摘要： A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.
摘要翻译：用于代码和数据存储的快闪存储器包括具有快速读取访问和用于执行的适用性的代码存储器阵列，具有低位成本和高密度存储的特性的数据存储器阵列，以及提供对两者的访问的适当接口代码和数据。代码存储器阵列可以是NOR阵列或性能增强的NAND阵列。存储器可以在单个芯片封装或多芯片封装解决方案中实现。

38. 发明授权

US07724071B2 Voltage boosting device and method for semiconductor device 有权
标题翻译：用于半导体器件的升压装置及方法
公开(公告)号：US07724071B2
公开(公告)日：2010-05-25
申请号：US11493467
申请日：2006-07-25
申请人： Akira Okada , Masaru Yano , Kazuhide Kurosaki
发明人： Akira Okada , Masaru Yano , Kazuhide Kurosaki
IPC分类号： G05F1/02
CPC分类号： G11C16/30 , G11C5/145
摘要： A semiconductor device includes: a pump circuit that boosts an output node connected to a memory cell array; an oscillator that outputs a clock to the pump circuit; and a detection circuit that outputs an actuating signal to the oscillator. In this semiconductor device, the actuating signal actuates the oscillator when the voltage of the output node of the pump circuit is lower than a first reference voltage, and the actuating signal stops the oscillator when the voltage of the output node is higher than a second reference voltage. In accordance with the present invention, when the voltage of the output node of the pump circuit is higher than the target voltage, the oscillator is stopped, and so is the pump circuit. Thus, unnecessary charge flow to the ground can be prevented, and the power consumption of the booster circuit can be reduced.
摘要翻译：一种半导体器件包括：泵电路，其对连接到存储单元阵列的输出节点进行升压; 一个向泵电路输出时钟的振荡器; 以及向振荡器输出启动信号的检测电路。在该半导体器件中，当泵电路的输出节点的电压低于第一参考电压时，致动信号致动振荡器，并且当输出节点的电压高于第二参考电压时，致动信号停止振荡器电压。根据本发明，当泵电路的输出节点的电压高于目标电压时，振荡器停止，泵电路停止。因此，可以防止不必要的电荷流向地面，并且可以降低升压电路的功耗。

39. 发明授权

US07468909B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07468909B2
公开(公告)日：2008-12-23
申请号：US11637260
申请日：2006-12-11
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C11/34 , G11C16/06 , G11C5/06
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明还提供一种控制半导体器件的方法。

40. 发明授权

US07385844B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07385844B2
公开(公告)日：2008-06-10
申请号：US11494872
申请日：2006-07-27
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491 , G11C2216/14
摘要： A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).
摘要翻译：半导体器件包括：存储单元阵列，其具有多个非易失性存储单元，每个非易失性存储单元在电荷存储层中的不同区域中具有第一位和第二位; 存储要写入存储单元阵列的数据的SRAM阵列（第一存储器单元）; WR读出放大器块（第二存储器单元），其将要写入第一位的第一划分数据和要写入第二位的第二划分数据存储，第一划分数据通过将数据划分为预定单位形成，第二划分数据通过将数据划分为预定单位形成分割数据; 以及将第一划分数据写入存储单元阵列的存储单元的第二位之后，将第二划分数据写入存储单元阵列的存储单元的第一位（步骤S28）的控制电路（步骤S 22）。

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