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31. 发明授权

US08438205B2 Exponentiation calculation apparatus and method for calculating square root in finite extension field 有权
公开(公告)号：US08438205B2
公开(公告)日：2013-05-07
申请号：US12393558
申请日：2009-02-26
申请人： Tomoko Yonemura , Hirofumi Muratani , Atsushi Shimbo , Kenji Ohkuma , Taichi Isogai , Yuichi Komano , Kenichiro Furuta , Yoshikazu Hanatani
发明人： Tomoko Yonemura , Hirofumi Muratani , Atsushi Shimbo , Kenji Ohkuma , Taichi Isogai , Yuichi Komano , Kenichiro Furuta , Yoshikazu Hanatani
IPC分类号： G06F17/10 , G06F7/38 , G06F7/52 , G06F7/50 , H04L9/28
CPC分类号： G06F17/10 , G06F7/724
摘要： In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.

32. 发明授权

US07826637B2 Digital watermark embedding apparatus, digital watermark detecting apparatus, digital watermark embedding method, digital watermark detecting method and computer program product 有权
标题翻译：数字水印嵌入装置，数字水印检测装置，数字水印嵌入方法，数字水印检测方法及计算机程序产品
公开(公告)号：US07826637B2
公开(公告)日：2010-11-02
申请号：US11336832
申请日：2006-01-23
申请人： Hirofumi Muratani
发明人： Hirofumi Muratani
IPC分类号： G06K9/00 , H04L9/32
CPC分类号： G06T1/0085 , G06T1/0064 , G06T2201/0061 , G10L19/018 , H04N1/32144 , H04N1/32267 , H04N1/32352 , H04N2201/3233 , H04N2201/327
摘要： A digital watermark embedding apparatus for embedding watermark information into a digital content, obtains a predetermined topological invariant corresponding to the watermark information to be embedded into the digital content, and sets the predetermined topological invariant to the digital content by modifying the digital content into which the watermark information is to be embedded.
摘要翻译：一种用于将水印信息嵌入数字内容的数字水印嵌入装置，获得与要嵌入到数字内容中的水印信息相对应的预定拓扑不变量，并通过修改数字内容来将预定拓扑不变量设置为数字内容，嵌入水印信息。

33. 发明申请

US20100046745A1 ENCRYPTING APPARATUS, DECRYPTING APPARATUS, CRYPTOCOMMUNICATION SYSTEM, AND METHODS AND COMPUTER PROGRAM PRODUCTS THEREFOR 审中-公开
标题翻译：加密设备，分解设备，CRYPTOCOMM通信系统及其计算机程序产品
公开(公告)号：US20100046745A1
公开(公告)日：2010-02-25
申请号：US12397668
申请日：2009-03-04
申请人： Yoshikazu Hanatani , Kenji Ohkuma , Atsushi Shimbo , Hirofumi Muratani , Taichi Isogai , Yuichi Komano , Kenichiro Furuta , Tomoko Yonemura
发明人： Yoshikazu Hanatani , Kenji Ohkuma , Atsushi Shimbo , Hirofumi Muratani , Taichi Isogai , Yuichi Komano , Kenichiro Furuta , Tomoko Yonemura
IPC分类号： H04L9/06
CPC分类号： H04L9/083 , H04L9/3073 , H04L2209/30
摘要： A decrypting apparatus that decrypts encrypted data that has been encrypted first data containing plain data, the encrypted data being represented by using an affine representation F_{p̂m}×F_{p̂m}̂*(where p: a prime number; m: a natural number; and ̂: exponentiation) obtains encrypted data represented in a vector format and a secret key corresponding to a public key and judges whether a vector component contained in the encrypted data is the affine representation F_{p̂m}×F_{p̂m}̂*. Further, based on the result of the judging process, the decrypting apparatus maps the vector component onto each of the members of an algebraic torus by forming a decompression map and decrypts the encrypted data mapped onto each of the members of the algebraic torus, by using the secret key, therefore obtains the plain data.
摘要翻译：一种解密装置，对已经加密的加密数据进行第一数据的解密，该数据包含普通数据，加密数据使用仿射表示法F_ {pm}×F_ {pm} *（其中p：素数; m：数字;和：取幂）获得以向量格式表示的加密数据和与公钥对应的秘密密钥，并且判断加密数据中包含的向量成分是否为仿射表示F_ {pm}×F_ {pm} * 。此外，基于判断处理的结果，解密装置通过形成解压缩映射将矢量分量映射到代数环面的每个成员上，并且通过使用映射到代数环面的每个成员的加密数据进行解密秘密密钥，因此获得普通数据。

34. 发明申请

US20090207999A1 DECRYPTION PROCESSING APPARATUS, SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译： DECRYPTION PROCESSING APPARATUS，SYSTEM，METHOD，AND COMPUTER PROGRAM PRODUCT
公开(公告)号：US20090207999A1
公开(公告)日：2009-08-20
申请号：US12346265
申请日：2008-12-30
申请人： Tomoko Yonemura , Hirofumi Muratani
发明人： Tomoko Yonemura , Hirofumi Muratani
IPC分类号： H04L9/06 , G06F17/30
CPC分类号： H04L9/08 , H04L9/3013 , H04L2209/30
摘要： In a decryption processing apparatus, a decompression processing unit performs a map to pieces of compressed data included in a compressed encrypted data, thereby obtaining the pieces of the encrypted data having each of the pieces of the compressed data decompressed, the decompression map being a process of inputting the compressed data and either the final output data or the auxiliary output data and being a process of outputting the encrypted data and the auxiliary output data, a decryption processing unit performs a decryption process to each of the pieces of encrypted data, using a secret key corresponding to the public key, thereby obtaining the plain data, and a control unit controls parallel execution of the decompression process and the decryption process, and controls the decryption process performed by the decryption processing unit to the encrypted data output by the decompression processing unit, based on the decryption procedure.
摘要翻译：在解密处理装置中，解压缩处理单元对包含在压缩加密数据中的压缩数据执行映射，从而获得压缩数据中的每一个被解压缩的加密数据，解压缩映射是处理输入压缩数据和最终输出数据或辅助输出数据，并且作为输出加密数据和辅助输出数据的处理，解密处理单元对每一个加密数据执行解密处理，使用秘密密钥对应于公开密钥，从而获得明文数据，并且控制单元控制解压缩处理和解密处理的并行执行，并且将由解密处理单元执行的解密处理控制为通过解压缩处理输出的加密数据单位，基于解密程序。

35. 发明授权

US07227948B2 Encryption apparatus and method, and decryption apparatus and method based on block encryption 有权
公开(公告)号：US07227948B2
公开(公告)日：2007-06-05
申请号：US09799028
申请日：2001-03-06
申请人： Kenji Ohkuma , Hirofumi Muratani , Shinichi Kawamura , Fumihiko Sano
发明人： Kenji Ohkuma , Hirofumi Muratani , Shinichi Kawamura , Fumihiko Sano
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L9/0631 , H04L9/0625 , H04L2209/08 , H04L2209/12 , H04L2209/24
摘要： An encryption apparatus for block data, comprises a first processing unit randomizing the block data in units of first portions obtained by dividing the block data, and a second processing unit diffusing the block data output from the first processing unit with respect to a second portion of the block data which is wider than the first portion. The first processing unit comprises first nonlinear processing units nonlinearly transforming the block data in units of the first portions. The second processing unit comprises a first linear diffusion processing unit linearly diffusing the second portion of the block data. At least one of the first nonlinear processing units comprises second nonlinear processing units nonlinearly transforming the block data in units of the first portions, and a second linear diffusion processing unit linearly diffusing the second portion of the block data.

36. 发明授权

US07123744B2 Digital watermark embedding method, digital watermark embedding apparatus, digital watermark detecting method, and digital watermark detecting apparatus 失效
公开(公告)号：US07123744B2
公开(公告)日：2006-10-17
申请号：US10305192
申请日：2002-11-27
申请人： Hirofumi Muratani , Tooru Kambayashi , Tomoo Yamakage , Shinichiro Koto , Tomoya Kodama , Hisashi Yamada
发明人： Hirofumi Muratani , Tooru Kambayashi , Tomoo Yamakage , Shinichiro Koto , Tomoya Kodama , Hisashi Yamada
IPC分类号： G06K9/00
CPC分类号： G06T1/0064 , G06T1/005 , G06T2201/0052 , G06T2201/0065 , G06T2201/0083
摘要： A digital watermark embedding apparatus comprises a digital watermark generating unit which transforms embedding target contents by using a filter having a coefficient with a periodic number sequence to generate a digital watermark, and an embedding unit which superposes the digital watermark on the embedding target contents to generate watermark embedded contents.

37. 发明授权

US06901515B1 Code generating method and unit thereof, code detecting method and unit thereof, and watermark embedding unit and watermark detecting unit 失效
标题翻译：代码生成方法及其单元，代码检测方法及其单元，以及水印嵌入单元和水印检测单元
公开(公告)号：US06901515B1
公开(公告)日：2005-05-31
申请号：US09658565
申请日：2000-09-08
申请人： Hirofumi Muratani
发明人： Hirofumi Muratani
IPC分类号： H04N7/24 , G06T1/00 , G10L19/018 , G10L25/51 , H04N1/32 , H04N1/387 , H04N7/08 , H04N7/081 , H04L9/00
CPC分类号： G06T1/005 , G06T2201/0063 , G10L19/018 , H04H20/31 , H04H2201/50 , H04N1/32144 , H04N2201/3226 , H04N2201/3236 , H04N2201/324 , H04N2201/327
摘要： Residue calculating sections respectively obtain residues which take a plurality of integers as modulus, with respect to a user ID. The plurality of integers are stored in modulus storage sections and are prime to each other. Based on these residues and parameters stored in a coding parameter storage section, component codes constructed by continuous sequences of 1 and 0 using a predetermined number of bits as a unit are respectively generated by component code generating sections. These component codes are concatenated by a concatenating section, thereby to obtain a code to be embedded, which constructs watermark information.
摘要翻译：相对于用户ID，残差计算部分别分别获得以多个整数为模数的残差。多个整数被存储在模数存储部分中并且彼此相互叠加。基于存储在编码参数存储部中的这些残留和参数，分量代码生成部分分别生成以预定位数为单位的由1和0的连续序列构成的分量代码。这些分量代码由级联部分连接，从而获得嵌入的代码，其构建水印信息。

38. 发明授权

US5572710A High speed logic simulation system using time division emulation suitable for large scale logic circuits 失效
标题翻译：高速逻辑仿真系统采用适合大规模逻辑电路的时分仿真
公开(公告)号：US5572710A
公开(公告)日：1996-11-05
申请号：US120220
申请日：1993-09-13
申请人： Shigehiro Asano , Shouzou Isobe , Jiro Amemiya , Hirofumi Muratani
发明人： Shigehiro Asano , Shouzou Isobe , Jiro Amemiya , Hirofumi Muratani
IPC分类号： G06F17/50 , G06F17/00 , G06F9/455
CPC分类号： G06F17/5027 , G06F17/5022 , Y10S706/92 , Y10S706/921
摘要： A logic simulation system capable of handling a very large scale circuit while realizing a high speed simulation by retaining the parallelism of the simulation targets. The system includes: a host computer having data of the simulation target divided into a plurality of sections defining different simulation phases to be executed sequentially in time division; an emulator for emulating the simulation target, including: a plurality of programmable emulation chips for mapping the simulation target, each emulation chip having a memory with a plurality of memory banks provided in correspondence to the plurality of sections for registering mapping data specifying a function to be realized by each emulation chip in emulating each of the plurality of sections; a programmable network for interconnecting the plurality of emulation chips; and an emulation control unit for controlling the plurality of emulation chips and the network by sequentially switching the memory banks of the memory of each emulation chip and changing connections among the plurality of emulation chips provided by the network in emulating each of the plurality of sections; and an interface unit for interfacing the host computer and the emulator.
摘要翻译：一种逻辑仿真系统，能够通过保持模拟目标的并行性实现高速仿真，处理大规模电路。该系统包括：具有模拟目标的数据的主计算机，被划分为定义不同模拟阶段的多个部分，以便按时间顺序执行; 用于仿真所述模拟目标的仿真器，包括：用于映射所述模拟目标的多个可编程仿真芯片，每个仿真芯片具有存储器，所述存储器具有与所述多个部分对应地设置的多个存储体，用于将指定功能的映射数据注册到每个仿真芯片在模拟多个部分中的每个部分时实现; 用于互连所述多个仿真芯片的可编程网络; 以及仿真控制单元，用于通过顺序地切换每个仿真芯片的存储器的存储器并且改变由所述网络提供的所述多个仿真芯片中的模拟所述多个部分中的每一个的连接，来控制所述多个仿真芯片和所述网络; 以及用于连接主计算机和仿真器的接口单元。

39. 发明授权

US08924448B2 Arithmetic device, method, and program product 有权
标题翻译：算术设备，方法和程序产品
公开(公告)号：US08924448B2
公开(公告)日：2014-12-30
申请号：US13422018
申请日：2012-03-16
申请人： Taichi Isogai , Kenichiro Furuta , Hirofumi Muratani , Kenji Ohkuma , Tomoko Yonemura , Yoshikazu Hanatani , Atsushi Shimbo , Hanae Ikeda , Yuichi Komano
发明人： Taichi Isogai , Kenichiro Furuta , Hirofumi Muratani , Kenji Ohkuma , Tomoko Yonemura , Yoshikazu Hanatani , Atsushi Shimbo , Hanae Ikeda , Yuichi Komano
IPC分类号： G06F7/58 , G06F7/00 , H04L9/28 , H04L9/00 , G06F7/72 , H04L9/30
CPC分类号： H04L9/003 , G06F7/725 , H04L9/3013
摘要： An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information.
摘要翻译：运算装置包括输入单元，输入作为组的要素的数据; 配置转换单元，当输入数据处于第二表示时，将输入数据转换为第一表示，并且使用第一表示中的操作数对转换的第一表示执行算术运算，其中至少一个子组件是零元素以将转换后的第一表示转换为以第一表示表示的第一转换数据，以及当输入数据处于第一表示时，使用第一表示中的操作数对输入数据执行算术运算，其中至少一个子组件是将输入数据转换成以第一表示表示的第二转换数据的零元素; 以及操作单元，其使用秘密信息对所述第一或第二转换数据执行算术处理。

40. 发明授权

US08533243B2 Representation converting apparatus, arithmetic apparatus, representation converting method, and computer program product 失效
标题翻译：表示转换装置，运算装置，表示转换方法和计算机程序产品
公开(公告)号：US08533243B2
公开(公告)日：2013-09-10
申请号：US12397648
申请日：2009-03-04
申请人： Tomoko Yonemura , Hirofumi Muratani , Kenji Ohkuma , Hanae Ikeda , Taichi Isogai , Kenichiro Furuta , Yoshikazu Hanatani
发明人： Tomoko Yonemura , Hirofumi Muratani , Kenji Ohkuma , Hanae Ikeda , Taichi Isogai , Kenichiro Furuta , Yoshikazu Hanatani
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F17/10
摘要： When converting an affine representation representing a 2r-th degree algebraic torus T2r(Fq) (r is a prime number, and q is an integer) to a projective representation representing a quadratic algebraic torus T2(Fq^r), a representation converting apparatus acquires member (c0, c1, . . . , cr-2), (ci is a member of a finite field Fq, where 0≦i≦r−2) of a 2r-th degree algebraic torus T2r(Fq) represented by the affine representation. The apparatus performs a multiplication operation on the acquired member. The multiplication operation is determined by a condition under which a member of a quadratic algebraic torus T2(Fq^r) is included in the 2r-th degree algebraic torus T2r(Fq), a modulus and a base of a quadratic extension, and a modulus and a base of an r-th degree extension. The representation converting apparatus then performs an addition and subtraction operation determined by the condition, the moduli, and the bases.
摘要翻译：当表示代表二次代数环面T2（Fq ^ r）的投影表示将表示2r次代数圆环T2r（Fq）（r是素数，q是整数）的仿射表示转换为表示转换装置获取成员（c0，c1，...，cr-2），（ci是有限域Fq的成员，其中0 @ i @ r-2）由2r代数圆环T2r（Fq）仿射表示。该装置对获取的成员进行乘法运算。乘法运算由二次代数圆环T2（Fq ^ r）的成员包含在第二阶代数圆环T2r（Fq）中的条件，二次扩展的模数和基数，以及模数和r度延伸的基数。然后，表示转换装置执行由条件，模数和基数确定的加法和减法运算。

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