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    • 33. 发明授权
      US5849615A Semiconductor processing method of fabricating field effect transistors 失效
    • Semiconductor processing method of fabricating field effect transistors
    • US5849615A
    • 1998-12-15
    • US604904
    • 1996-02-22
    • Aftab Ahmad , Kirk Prall
    • Aftab Ahmad , Kirk Prall
    • H01L21/336 , H01L21/8238
    • H01L29/6653 , H01L21/823814
    • In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 34. 发明授权
      US5716862A High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS 失效
    • High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS
    • 采用分裂多晶硅CMOS工艺的高性能PMOSFET，包含用于制造多兆位DRAMS的先进的堆叠电容单元
    • US5716862A
    • 1998-02-10
    • US491179
    • 1995-06-16
    • Aftab Ahmad , Randhir P. S. Thakur , Kirk Prall , Tyler Lowrey , Brett Rolfson
    • Aftab Ahmad , Randhir P. S. Thakur , Kirk Prall , Tyler Lowrey , Brett Rolfson
    • H01L21/28 , H01L21/265 , H01L21/02 , H01L21/70 , H01L27/00
    • H01L21/28061 , H01L21/28247
    • This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600.degree.-957.degree. C., to form poly gate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes; and performing a p-type impurity implant into the n-well regions.
    • 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。 在本发明的一个实施例中，教导了通过以下步骤形成p沟道器件的半导体制造工艺：定义在n-阱区上具有基本上垂直的侧壁的p沟道晶体管栅电极; 对n阱区域进行p型杂质注入，以在每个p沟道晶体管栅电极的相对侧上形成p沟道源极和漏极端子; 在n阱区域中执行倾斜的n型杂质注入以在p沟道源极和漏极端子周围形成n型光晕; 在600〜957℃的温度范围内进行低温氧化步骤，以形成围绕p沟道晶体管栅极垂直侧壁的多晶硅侧壁氧化; 以及对n阱区进行p型杂质注入。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 35. 发明授权
      US5494841A Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells 失效
    • Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells
    • 分层多晶硅CMOS工艺，用于结合堆叠容器电容器单元的多兆位动态存储器
    • US5494841A
    • 1996-02-27
    • US322807
    • 1994-10-13
    • Charles H. Dennison , Aftab Ahmad
    • Charles H. Dennison , Aftab Ahmad
    • H01L27/092 , H01L21/8238 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
    • H01L27/10852 , H01L21/8238 , H01L27/105
    • This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. The focus of this invention is a CMOS manufacturing process flow which permits P-channel source/drain doping subsequent to capacitor formation. A main feature of the process is the deposition and planarization of a thick insulative mold layer subsequent to N-channel device patterning, but prior to P-channel device patterning. In one embodiment of the process, portions of this insulative layer overlying the P-channel transistor regions are removed during the storage-node contact etch. Thus, a low-aspect-ratio etch can be employed to pattern P-channel devices, and a blanket P+ implant may be performed without implanting the P-type impurity into source/drain regions of the N-channel devices. Another important feature of the invention is the incorporation of P-channel gate sidewall spacers and offset P-channel implants into the process flow.
    • 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。 本发明的重点是CMOS制造工艺流程，其允许电容器形成之后的P沟道源极/漏极掺杂。 该工艺的主要特征是在N沟道器件图案化之后，但在P沟道器件图案化之前，沉积和平坦化厚的绝缘模具层。 在该过程的一个实施例中，在存储节点接触蚀刻期间，去除覆盖在P沟道晶体管区域上的该绝缘层的部分。 因此，可以采用低纵横比蚀刻图案P沟道器件，并且可以执行覆盖P +注入而不将P型杂质注入到N沟道器件的源极/漏极区域中。 本发明的另一个重要特征是将P沟道栅极侧壁间隔物和偏移P沟道植入物结合到工艺流程中。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 36. 发明授权
      US5489546A Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process 失效
    • Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process
    • 在分裂多晶硅DRAM工艺中使用独立厚度间隔物形成CMOS器件的方法
    • US5489546A
    • 1996-02-06
    • US449300
    • 1995-05-24
    • Aftab Ahmad , Pierre C. Fazan , Charles H. Dennison
    • Aftab Ahmad , Pierre C. Fazan , Charles H. Dennison
    • H01L21/8238 , H01L21/8242
    • H01L21/823864
    • NMOS and PMOS devices are formed in a split-polysilicon CMOS process using independent thickness transistor gate spacers, and using a silicon nitride layer as a mask for the p-channel region during an n+ source/drain implant step of the n-channel region. The p-channel spacer is formed significantly thicker than the n-channel spacer, thereby reducing lateral diffusion of p-type dopant species under the p-channel gate and avoiding short channel effects to improve device reliability and performance. P-channel transistor junction depth and lateral diffusion is further reduced by performing an n-channel arsenic source/drain implant before the p-channel source/drain boron difluoride implant, although the p-channel transistor gate is etched before the n-channel gate. Moreover, since the p-channel transistor gate is etched before the n-channel gate, the p-channel gate sidewalls are reoxidized as well as the n-channel gate sidewalls for improved gate oxide integrity.
    • 使用独立厚度的晶体管栅极隔离器，在分离多晶硅CMOS工艺中形成NMOS和PMOS器件，并且在n沟道区域的n +源极/漏极注入步骤期间使用氮化硅层作为p沟道区的掩模。 p沟道间隔物形成为比n沟道间隔物显着更厚，从而减少p型掺杂剂物质在p沟道栅极下的横向扩散，并且避免短沟道效应以提高器件的可靠性和性能。 尽管p沟道晶体管栅极在n沟道栅极之前被蚀刻，但是在p沟道源极/漏极二硼化硼注入之前执行n沟道砷源极/漏极注入来进一步减小P沟道晶体管结深度和横向扩散。 。 此外，由于在n沟道栅极之前蚀刻p沟道晶体管栅极，所以p沟道栅极侧壁以及n沟道栅极侧壁被再氧化以改善栅极氧化物的完整性。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 37. 发明授权
      US5338700A Method of forming a bit line over capacitor array of memory cells 失效
    • Method of forming a bit line over capacitor array of memory cells
    • 在存储器单元的电容器阵列上形成位线的方法
    • US5338700A
    • 1994-08-16
    • US47668
    • 1993-04-14
    • Charles H. Dennison , Aftab Ahmad
    • Charles H. Dennison , Aftab Ahmad
    • H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/72
    • H01L27/10852 , H01L21/768 , H01L27/10808 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
    • A method of forming a bit line over capacitor array of memory cells includes providing first conductive material pillars within first contact openings downwardly to active (source/drain) areas for ultimate connection with bit lines. A covering layer of insulating material is provided over the first pillars, and contact openings provided therethrough to electrically connect with other active (source/drain) areas for formation of capacitors. Capacitors are then provided within the capacitor contact openings. An overlying layer of insulating material is then provided over the covering layer of insulating material and over the capacitors. Bit line contact openings are then provided through the overlying layer and the covering layer to the first pillar upper surfaces. Then, a digit line layer of conductive material is provided atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.
    • 在存储器单元的电容器阵列上形成位线的方法包括：将第一接触开口内的第一导电材料柱向下提供到用于与位线最终连接的有源（源极/漏极）区域。 绝缘材料的覆盖层设置在第一柱上，并且穿过其设置的接触开口与其他有源（源极/漏极）区域电连接以形成电容器。 然后在电容器接触开口内提供电容器。 然后在绝缘材料的覆盖层上和电容器上方覆盖绝缘材料层。 然后将位线接触开口穿过覆盖层和覆盖层提供到第一柱上表面。 然后，导电材料的数字线层被提供在晶片顶部和位线接触开口内，数字线层与第一柱上表面电连接。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 40. 发明申请
      US20050012158A1 Locos trench isolation structure 审中-公开
    • Locos trench isolation structure
    • Locos沟槽隔离结构
    • US20050012158A1
    • 2005-01-20
    • US10899609
    • 2004-07-27
    • Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
    • Fernando Gonzalez , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
    • H01L21/762 , H01L29/76
    • H01L21/76202 , H01L21/76221 , Y10S148/05
    • A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
    • 通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。 回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。 通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。 然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。 在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。 或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。 再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。 或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。 由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。 该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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