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31. 发明申请

US20070079204A1 Integrated Circuit Testing Module Including Signal Shaping Interface 有权
标题翻译：集成电路测试模块包括信号整形接口
公开(公告)号：US20070079204A1
公开(公告)日：2007-04-05
申请号：US11552938
申请日：2006-10-25
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31928 , G06F11/263 , G11C29/14 , G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.
摘要翻译：公开了测试集成电路的系统和方法。这些系统包括配置成在自动测试设备和要测试的集成电路之间运行的测试模块。测试接口被配置为以比从自动测试设备接收信号的转换速率更高的转换速率测试集成电路。为了这样做，测试接口包括被配置用于生成要传送到集成电路的地址，命令和测试数据的组件。可以生成各种测试数据模式，并且测试数据可以取决于地址。系统可选地被配置为包括被配置为存储一个或多个测试计划的测试计划存储器组件。测试计划可以包括一系列测试模式和/或条件分支，由此下一步执行的测试取决于前面测试的结果。测试计划存储器可选地可从测试模块拆卸。

32. 发明申请

US20050204223A1 Bonding pads for testing of a semiconductor device 有权
公开(公告)号：US20050204223A1
公开(公告)日：2005-09-15
申请号：US11108385
申请日：2005-04-18
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/28
CPC分类号： G01R31/2884 , H01L2224/05554 , H01L2224/48111 , H01L2224/48137 , H01L2224/48139
摘要： A first integrated circuit chip is provided for packaging along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and the second integrated circuit chips, wherein the first integrated circuit chip is designed for normal operation and a test mode. The first integrated circuit chip includes up to eleven bonding pads for complete testing of the first integrated circuit chip, wherein the up to eleven bonding pads are for communicating TEST, SET, LOAD, and up to eight TDQ signals. The TEST, SET, and LOAD signals are operable to transition the first integrated circuit chip from normal operation into the test mode and to enable test codes to be loaded into the first integrated circuit chip during a programming phase of the test mode. The up to eight TDQ signals are operable to load test codes into the first integrated circuit during the programming phase of the test mode and to read/write data to and from the first integrated circuit chip during an access phase of the test mode.

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