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31. 发明授权

US09040387B2 Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof 有权
公开(公告)号：US09040387B2
公开(公告)日：2015-05-26
申请号：US13591969
申请日：2012-08-22
申请人： Zhiwei Gong , Michael B Vincent , Scott M Hayes , Jason R Wright
发明人： Zhiwei Gong , Michael B Vincent , Scott M Hayes , Jason R Wright
IPC分类号： H01L21/30 , H01L23/538 , H01L21/78 , H01L23/48 , H01L23/31 , H01L23/498 , H01L21/56 , H01L25/10 , H01L23/00
摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

32. 发明授权

US09036363B2 Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication 有权
标题翻译：器件和具有平行导体和导体间隔离器结构的堆叠微电子封装及其制造方法
公开(公告)号：US09036363B2
公开(公告)日：2015-05-19
申请号：US14042623
申请日：2013-09-30
申请人： Michael B. Vincent , Zhiwei Gong
发明人： Michael B. Vincent , Zhiwei Gong
IPC分类号： H05K7/00 , H05K1/11 , H05K1/18 , H05K3/10 , H05K3/32
CPC分类号： H01L23/3114 , H01L23/49805 , H01L24/19 , H01L2224/04105 , H01L2225/1035 , H01L2225/1064 , H01L2225/1076 , H01L2924/12042 , H01L2924/1815 , Y10T29/4913 , H01L2924/00
摘要： Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.
摘要翻译：装置及其制造方法的实施例包括将第一和第二封装表面导体耦合到封装表面，并在封装表面导体之间具有导体内绝缘结构。封装表面导体在封装表面露出的焊垫组之间延伸并电耦合。包装表面导体的细长部分彼此平行并相邻。导体内绝缘结构沿着整个平行和相邻的细长部分耦合在封装表面导体之间，并且导体内绝缘结构将封装表面导体的细长部分彼此电绝缘。一些实施例可以结合堆叠的微电子封装来实现，该堆叠式微电子封装包括侧壁导体和导体间绝缘结构，并且使侧壁导体彼此电绝缘。

33. 发明申请

US20150108621A1 SHIELDED DEVICE PACKAGES AND RELATED FABRICATION METHODS 审中-公开
标题翻译：屏蔽器件封装及相关制造方法
公开(公告)号：US20150108621A1
公开(公告)日：2015-04-23
申请号：US14056644
申请日：2013-10-17
申请人： EDUARD J. PABST , ZHIWEI GONG
发明人： EDUARD J. PABST , ZHIWEI GONG
IPC分类号： H01L23/552 , H01L23/492 , H01L23/31 , H01L21/56
CPC分类号： H01L23/552 , H01L21/568 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L24/19 , H01L24/73 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/00012 , H01L2924/014 , H01L2924/00
摘要： Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a frame structure circumscribing the one or more electrical components, and a shielding structure overlying the frame structure and the one or more electrical components. The shielding structure contacts a first surface of the frame structure, at least a portion of the molding compound resides between the shielding structure and the one or more electrical components, and the first surface of the frame structure is aligned with a second surface of the portion of the molding compound.
摘要翻译：提供了屏蔽器件封装和相关的制造方法。示例性的器件封装包括一个或多个电气部件，覆盖一个或多个电气部件的模制化合物，围绕所述一个或多个电气部件的框架结构以及覆盖所述框架结构和所述一个或多个电气部件的屏蔽结构。屏蔽结构接触框架结构的第一表面，模制化合物的至少一部分位于屏蔽结构和一个或多个电气部件之间，并且框架结构的第一表面与该部分的第二表面对准的模塑料。

34. 发明授权

US09000589B2 Semiconductor device with redistributed contacts 有权
标题翻译：半导体器件具有重新分配的触点
公开(公告)号：US09000589B2
公开(公告)日：2015-04-07
申请号：US13483064
申请日：2012-05-30
申请人： Dominic Poh Meng Koey , Zhiwei Gong
发明人： Dominic Poh Meng Koey , Zhiwei Gong
IPC分类号： H01L23/48 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L21/56 , H01L21/561 , H01L23/3128 , H01L24/19 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices.
摘要翻译：通过在半导体管芯之间和之外定位具有金属接地平面构件阵列的半导体管芯阵列来组装表面贴装半导体器件。模具阵列和接地平面构件被封装在模塑料中。在模具和接地平面构件阵列上形成再分布层。再分配层在绝缘材料层内具有一组再分布导体。再分布导体将模具的电触点与器件的外部电接触元件互连。随着多个装置同时形成，相邻的装置通过沿模具之间的锯条切割而分离（分割）。模制化合物插入在接地平面构件的连接杆之间以及在锯道中的再分配层的绝缘材料以及分割装置的侧表面处。

35. 发明申请

US20130113091A1 METHOD OF PACKAGING SEMICONDUCTOR DIE 有权
标题翻译：包装半导体器件的方法
公开(公告)号：US20130113091A1
公开(公告)日：2013-05-09
申请号：US13292103
申请日：2011-11-09
申请人： Dominic Koey Poh Meng , Zhiwei Gong , Kesvakumar V.C. Muniandy , Weng Foong Yap
发明人： Dominic Koey Poh Meng , Zhiwei Gong , Kesvakumar V.C. Muniandy , Weng Foong Yap
IPC分类号： H01L23/28 , B29C33/12 , H01L21/56
CPC分类号： H01L23/49816 , H01L21/561 , H01L21/568 , H01L23/24 , H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/97 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2924/12042 , H01L2924/15787 , H01L2924/15788 , H01L2924/00
摘要： A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.
摘要翻译：封装半导体管芯的方法包括使用嵌入式接地层或嵌入式嵌入式单元。嵌入式单元是具有至少一个空腔的单个独立单元。嵌入式单元被放置在过程安装表面的封装区域内和之内。嵌入式单元可以具有不同的尺寸和形状以及在处理半导体管芯期间可以放置在基板，面板或带上的预定位置中的多个不同的空腔，该半导体管芯嵌入到再分布芯片封装（RCP）或晶片级封装 WFL）面板。嵌入式单元提供功能和设计灵活性，可以在单个处理面板或批次中运行多个嵌入式单元和半导体管芯或具有不同尺寸和尺寸的部件，并减少封装和封装后固化期间的裸片漂移，移动或偏斜。

36. 发明申请

US20130049218A1 SEMICONDUCTOR DEVICE PACKAGING HAVING PRE-ENCAPSULATION THROUGH VIA FORMATION 审中-公开
标题翻译：具有通过形成的预封装的半导体器件封装
公开(公告)号：US20130049218A1
公开(公告)日：2013-02-28
申请号：US13222150
申请日：2011-08-31
申请人： Zhiwei Gong , Navjot Chhabra , Glenn G. Daves , Scott M. Hayes
发明人： Zhiwei Gong , Navjot Chhabra , Glenn G. Daves , Scott M. Hayes
IPC分类号： H01L21/77 , H01L21/56 , H01L23/48
CPC分类号： H01L24/19 , H01L21/568 , H01L23/3128 , H01L24/96 , H01L2224/12105 , H01L2924/01012 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H05K1/185 , H05K3/4602 , H05K2203/0733 , H01L2924/00
摘要： A method for forming signal conduits before encapsulation for incorporation as through vias in a semiconductor device package is provided. One or more signal conduits are formed through photolithography and metal deposition on a metal film or substrate. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die and other parts of the package. The ends of the signal conduits are exposed and the signal conduits can then be used as through vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package, and electrical contacts of the semiconductor die. Using this method, signal conduits can be provided in a variety of geometric placings in the semiconductor device package. A semiconductor device package including the signal conduits made from the above method is also provided.
摘要翻译：提供了一种用于在封装之前形成信号导管以在半导体器件封装中通过通孔并入的方法。通过光刻和金属沉积在金属膜或衬底上形成一个或多个信号导管。在除去光致抗蚀材料之后，通过封装信号导管以及任何半导体管芯和封装的其它部分来构建半导体器件封装。信号管道的端部被暴露，然后可以将信号导管用作通孔，在封装的底部和顶部上的互连或触点之间提供信号承载通路，以及半导体管芯的电触头。使用该方法，信号导管可以以半导体器件封装中的各种几何布置提供。还提供了包括由上述方法制成的信号导管的半导体器件封装。

37. 发明授权

US08216918B2 Method of forming a packaged semiconductor device 有权
标题翻译：形成封装半导体器件的方法
公开(公告)号：US08216918B2
公开(公告)日：2012-07-10
申请号：US12842562
申请日：2010-07-23
申请人： Zhiwei Gong , Scott M. Hayes , George R. Leal , Douglas G. Mitchell , Jason R. Wright , Jianwen Xu
发明人： Zhiwei Gong , Scott M. Hayes , George R. Leal , Douglas G. Mitchell , Jason R. Wright , Jianwen Xu
IPC分类号： H01L21/00 , H01L21/322
CPC分类号： H01L21/6835 , H01L24/19 , H01L2221/68345 , H01L2224/12105 , H01L2224/16235 , H01L2224/24137 , H01L2224/24227 , H01L2225/1035 , H01L2924/01029 , H01L2924/15311 , H01L2924/18162 , H01L2924/3511 , H05K1/185 , H05K2203/1469
摘要： A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.
摘要翻译：使用一种方法来形成封装的半导体器件。具有活性表面的半导体器件被放置在电路板的开口中。电路板具有第一主表面和具有开口的第二主表面，在第一主表面和第二主表面之间延伸的第一通孔，第一接触垫在第一主表面处终止通孔，第二接触垫终止第二个主要表面的通孔。电介质层被施加在半导体器件和电路板的第二主表面上。在电介质层上形成互连层。互连层具有电连接到第二接触焊盘的第二通孔，电连接到半导体器件的有源表面的第三通孔，暴露表面和暴露表面处的第三接触焊盘。

38. 发明授权

US09673150B2 EMI/RFI shielding for semiconductor device packages 有权
公开(公告)号：US09673150B2
公开(公告)日：2017-06-06
申请号：US14571878
申请日：2014-12-16
申请人： Zhiwei Gong , Scott M. Hayes , Michael B. Vincent
发明人： Zhiwei Gong , Scott M. Hayes , Michael B. Vincent
IPC分类号： H01L23/34 , H01L23/552 , H01L23/495 , H01L23/31 , H01L21/56 , H01L21/78 , H01L21/3205 , H01L23/00 , H01L23/498
CPC分类号： H01L23/552 , H01L21/3205 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3114 , H01L23/49524 , H01L23/49541 , H01L23/49827 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L24/96 , H01L24/97 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/12105 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/207 , H01L2924/3025 , H01L2224/83 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015
摘要： An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

39. 发明申请

US20160172309A1 EMI/RFI SHIELDING FOR SEMICONDUCTOR DEVICE PACKAGES 有权
标题翻译： EMI / RFI屏蔽用于半导体器件封装
公开(公告)号：US20160172309A1
公开(公告)日：2016-06-16
申请号：US14571878
申请日：2014-12-16
申请人： Zhiwei Gong , Scott M. Hayes , Michael B. Vincent
发明人： Zhiwei Gong , Scott M. Hayes , Michael B. Vincent
IPC分类号： H01L23/552 , H01L23/00 , H01L21/3205 , H01L21/56 , H01L21/78 , H01L23/495 , H01L23/31
CPC分类号： H01L23/552 , H01L21/3205 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3114 , H01L23/49524 , H01L23/49541 , H01L23/49827 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L24/96 , H01L24/97 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/12105 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/207 , H01L2924/3025 , H01L2224/83 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015
摘要： An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.
摘要翻译：一种封装的半导体器件封装，其具有与封装的侧面处的接地导电部件的端部接触的上覆导电EMI或RFI屏蔽以及制造半导体器件封装的方法。

40. 发明授权

US09257415B2 Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof 有权
公开(公告)号：US09257415B2
公开(公告)日：2016-02-09
申请号：US14706359
申请日：2015-05-07
申请人： Michael B. Vincent , Scott M. Hayes , Jason R. Wright , Zhiwei Gong
发明人： Michael B. Vincent , Scott M. Hayes , Jason R. Wright , Zhiwei Gong
IPC分类号： H01L23/00 , H01L25/065 , H01L23/498 , H01L23/538 , H01L25/10 , H01L23/31 , H01L21/56 , H01L21/48 , H01L25/00 , H01L25/03
CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/561 , H01L23/3107 , H01L23/3128 , H01L23/49805 , H01L23/49811 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/03 , H01L25/105 , H01L25/50 , H01L2225/06551 , H01L2225/1035 , H01L2225/1064 , H01L2924/12042 , H01L2924/1461 , H01L2924/00
摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

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