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    • 31. 发明申请
    • INFORMATION PROCESSING APPARATUS
    • 信息处理装置
    • US20120173850A1
    • 2012-07-05
    • US13423145
    • 2012-03-16
    • Teppei HIROTSUYuuichi ABETakeshi KATAOKAYasuhiro NAKATSUKA
    • Teppei HIROTSUYuuichi ABETakeshi KATAOKAYasuhiro NAKATSUKA
    • G06F9/38G06F13/40G06F9/312
    • G06F9/30054G06F9/3804G06F9/382
    • A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
    • 能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。 它是配备有CPU,存储器,预取装置等的信息处理装置,其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支 从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址,从而期待分支目的地址。 信息处理装置还包括RTS指令缓冲器,用于存储RTS指令的返回目的地的一系列指令,存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。