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31. 发明授权

US07218153B2 Word line driver with reduced leakage current 有权
标题翻译：具有减少漏电流的字线驱动器
公开(公告)号：US07218153B2
公开(公告)日：2007-05-15
申请号：US11208575
申请日：2005-08-22
申请人： Yen-Huei Chen
发明人： Yen-Huei Chen
IPC分类号： H03K19/094 , H03K19/21
CPC分类号： H03K19/0016
摘要： A circuit system having a first inverter, a second inverter and a blockage module is disclosed. The first inverter is coupled between a supply voltage and a complementary input signal, for generating a first output signal on an output terminal thereof in response to an input signal received by an input terminal of the same. The blockage module is coupled to the output terminal of the first inverter for selectively passing the first output signal there across in response to the input signal and the complementary input signal. The second inverter is coupled between the supply voltage and a complementary supply voltage, having a first input terminal directly coupled to the output terminal of the first inverter and a second input terminal coupled to the same via the blockage module for generating a second output signal in response to the first output signal.
摘要翻译：公开了一种具有第一逆变器，第二逆变器和阻塞模块的电路系统。第一反相器耦合在电源电压和互补输入信号之间，用于响应于由其输入端子接收的输入信号在其输出端产生第一输出信号。阻塞模块耦合到第一逆变器的输出端，用于响应于输入信号和互补输入信号选择性地使第一输出信号跨越。第二反相器耦合在电源电压和互补电源电压之间，具有直接耦合到第一反相器的输出端的第一输入端和经由阻塞模块耦合到第一反相器的第二输入端，用于产生第二输出信号响应第一个输出信号。

32. 发明授权

US08670637B2 Optical clock signal distribution using through-silicon vias 有权
标题翻译：光时钟信号分布采用硅通孔
公开(公告)号：US08670637B2
公开(公告)日：2014-03-11
申请号：US13209228
申请日：2011-08-12
申请人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
发明人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
IPC分类号： G02B6/12
CPC分类号： G02B6/43 , G06F1/105
摘要： An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.
摘要翻译：集成电路结构包括：包括前表面和后表面的半导体芯片; 从半导体芯片的背面延伸到半导体芯片的通孔，其中所述通孔是透光的; 和半导体芯片中的光子检测器，并暴露于通孔。

33. 发明申请

US20140022852A1 DATA INVERSION FOR DUAL-PORT MEMORY 有权
标题翻译：双端口存储器的数据反相
公开(公告)号：US20140022852A1
公开(公告)日：2014-01-23
申请号：US13552692
申请日：2012-07-19
申请人： Tzu-Kuei LIN , Jonathan Tsung-Yung CHANG , Hung-Jen LIAO , Yen-Huei CHEN , Jhon Jhy LIAW
发明人： Tzu-Kuei LIN , Jonathan Tsung-Yung CHANG , Hung-Jen LIAO , Yen-Huei CHEN , Jhon Jhy LIAW
IPC分类号： G11C8/16 , G11C7/10
CPC分类号： G11C7/1006 , G11C7/1075 , G11C8/16 , G11C11/412
摘要： A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.
摘要翻译：半导体存储器包括每个包括第一和第二端口的第一和第二存储器存储器锁存器。第一对位线耦合到第一端口，并且第二对位线耦合到第二端口。第一和第二对位线在第一和第二存储器锁存器之间被扭转。第一读出放大器耦合到第一对位线，用于输出数据，第二读出放大器耦合到第二对位线，用于输出中间数据信号。输出逻辑电路耦合到第二读出放大器的输出，并且被配置为基于中间数据信号和控制信号输出数据，该控制信号识别数据是否正在从第一存储器存储锁存器或第二存储器存储器锁存器中读取。

34. 发明授权

US08455354B2 Layouts of POLY cut openings overlapping active regions 有权
标题翻译： POLY切割开口与活跃区域重叠的布局
公开(公告)号：US08455354B2
公开(公告)日：2013-06-04
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

35. 发明授权

US08391097B2 Memory word-line driver having reduced power consumption 有权
标题翻译：存储器字线驱动器具有降低的功耗
公开(公告)号：US08391097B2
公开(公告)日：2013-03-05
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

36. 发明申请

US20110292754A1 MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的存储器字线驱动器
公开(公告)号：US20110292754A1
公开(公告)日：2011-12-01
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C8/08
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

37. 发明授权

US08005326B2 Optical clock signal distribution using through-silicon vias 有权
标题翻译：光时钟信号分布采用硅通孔
公开(公告)号：US08005326B2
公开(公告)日：2011-08-23
申请号：US12170570
申请日：2008-07-10
申请人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
发明人： Shih-Cheng Chang , Jin-Lien Lin , Kuo-Ching Hsu , Kai-Ming Ching , Jiun Yi Wu , Yen-Huei Chen
IPC分类号： G02B6/12
CPC分类号： G02B6/43 , G06F1/105
摘要： An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.
摘要翻译：集成电路结构包括：包括前表面和后表面的半导体芯片; 从半导体芯片的背面延伸到半导体芯片的通孔，其中所述通孔是透光的; 和半导体芯片中的光子检测器，并暴露于通孔。

38. 发明申请

US20100124099A1 8T LOW LEAKAGE SRAM CELL 有权
标题翻译： 8T低漏电SRAM单元
公开(公告)号：US20100124099A1
公开(公告)日：2010-05-20
申请号：US12273959
申请日：2008-11-19
申请人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
发明人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管，分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

39. 发明授权

US08767493B2 SRAM differential voltage sensing apparatus 有权
标题翻译： SRAM差分电压检测装置
公开(公告)号：US08767493B2
公开(公告)日：2014-07-01
申请号：US13169511
申请日：2011-06-27
申请人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
发明人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/062 , G11C11/419
摘要： An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.
摘要翻译： SRAM差分电压感测装置耦合到存储器电路。存储器电路包括存储体，多个位线，经由多个传输门和读出放大器耦合到多个位线的多条数据线。当感测放大器在表征模式下工作时，传输门和预充电电路被关断。差分电压感测装置将表征信号应用于感测放大器，并通过试错过程获得存储器电路的参数。

40. 发明授权

US08723265B2 Semiconductor structure with dummy polysilicon lines 有权
标题翻译：具有虚设多晶硅线的半导体结构
公开(公告)号：US08723265B2
公开(公告)日：2014-05-13
申请号：US13158133
申请日：2011-06-10
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： H01L21/70 , H01L27/32
CPC分类号： H01L27/0207 , H01L27/088 , H01L27/1104
摘要： A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.
摘要翻译：多指结构包括放置在一对虚拟POLY线之间的多个有源区域。有源区域包括多个多指状NMOS晶体管，它们是SRAM存储器电路的读出放大器的一部分。每个多指尖的NMOS晶体管的漏极和源极具有SiP / SiC外延生长区域。有源区域与虚拟POLY线路延伸并重叠。有源区域和虚拟POLY线之间的重叠有助于减少有源区域边缘处的边缘缺陷。

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