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    • 34. 发明授权
    • Power supplying circuit and phase-change random access memory including the same
    • 供电电路和包括相同的相变随机存取存储器
    • US07817489B2
    • 2010-10-19
    • US12251761
    • 2008-10-15
    • Beak-hyung ChoKwang-ho KimWon-seok Lee
    • Beak-hyung ChoKwang-ho KimWon-seok Lee
    • G11C5/14
    • G11C5/145G11C13/0004G11C13/0038
    • A power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks.
    • 供电电路(PSC)和包括PSC的相变随机存取存储器(PRAM)。 根据本发明的一个方面,PSC包括:第一电压发生器,被配置为将第一电压输出到第一端子; 以及第二电压发生器,被配置为向第二端子输出第二电压,所述第二电压发生器包括:电压泵单元,被配置为基于时钟信号和泵控制信号输出所述第二电压; 耦合到所述电压泵单元的泵输出检测器,所述泵输出检测器被配置为输出泵输出检测信号; 以及耦合到所述电压泵单元的放电单元,所述放电单元被配置为响应于放电信号将所述第二电压的电平放电到预定电平。 本发明的实施例可以防止由于提供给PRAM单元块的电压的电平的变化而可能发生的写入和/或读取故障。
    • 37. 发明申请
    • Memory card and memory storage device using the same
    • 存储卡和存储设备使用相同
    • US20090164722A1
    • 2009-06-25
    • US12314320
    • 2008-12-08
    • Won-Seok LeeJong-Keun Ahn
    • Won-Seok LeeJong-Keun Ahn
    • G06F12/00G06F13/00
    • G06F13/387G06F12/06Y02D10/13Y02D10/14Y02D10/151
    • A memory card and a memory storage device using the memory card may be provided. The memory card may include a host connector, a memory controller connected to the host connector and enabled or disabled in response to a capacity expansion signal, a non-volatile memory connected to the memory controller, a memory connector configured to connect to the memory controller and the non-volatile memory, and a capacity expansion switch configured to generate the capacity expansion signal. Accordingly, when the memory cards are connected to increase storage capacity, only a memory controller of one memory card may operate, thereby reducing power consumption.
    • 可以提供使用存储卡的存储卡和存储器存储装置。 存储卡可以包括主机连接器,连接到主机连接器并且响应于容量扩展信号而被启用或禁用的存储器控​​制器,连接到存储器控制器的非易失性存储器,被配置为连接到存储器控制器的存储器连接器 和非易失性存储器,以及容量扩展开关,其被配置为生成容量扩展信号。 因此,当存储卡被连接以增加存储容量时,只有一个存储卡的存储器控​​制器可以操作,从而降低功耗。
    • 38. 发明申请
    • POWER SUPPLYING CIRCUIT AND PHASE-CHANGE RANDOM ACCESS MEMORY INCLUDING THE SAME
    • 电源电路和相位变化随机存取存储器
    • US20090122601A1
    • 2009-05-14
    • US12251761
    • 2008-10-15
    • Beak-hyung CHOKwang-ho KIMWon-seok LEE
    • Beak-hyung CHOKwang-ho KIMWon-seok LEE
    • G11C11/00G11C7/00G11C8/00G11C5/14
    • G11C5/145G11C13/0004G11C13/0038
    • Embodiments of the invention provide a power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks.
    • 本发明的实施例提供了一种包括PSC的供电电路(PSC)和相变随机存取存储器(PRAM)。 根据本发明的一个方面,PSC包括:第一电压发生器,被配置为将第一电压输出到第一端子; 以及第二电压发生器,被配置为向第二端子输出第二电压,所述第二电压发生器包括:电压泵单元,被配置为基于时钟信号和泵控制信号输出所述第二电压; 耦合到所述电压泵单元的泵输出检测器,所述泵输出检测器被配置为输出泵输出检测信号; 以及耦合到所述电压泵单元的放电单元,所述放电单元被配置为响应于放电信号将所述第二电压的电平放电到预定电平。 本发明的实施例可以防止由于提供给PRAM单元块的电压的电平的变化而可能发生的写入和/或读取故障。
    • 40. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME
    • 半导体存储器件及其数据错误检测及校正方法
    • US20080109700A1
    • 2008-05-08
    • US11773214
    • 2007-07-03
    • Kwang-Jin LeeWon-Seok LeeDu-Eung Kim
    • Kwang-Jin LeeWon-Seok LeeDu-Eung Kim
    • G06F11/10
    • G06F11/1008G06F11/1076G11C8/04G11C8/12
    • A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
    • 半导体存储器件包括存储单元阵列,模式设置电路,奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据,响应于第二标志信号生成相对于正常写入数据的奇偶校验数据,并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据,响应于第二标志信号检测正常读取数据的错误,当错误为 检测并输出校正的读取数据。