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31. 发明申请

US20060033573A1 Amplifying circuit 有权
标题翻译：放大电路
公开(公告)号：US20060033573A1
公开(公告)日：2006-02-16
申请号：US10537470
申请日：2003-12-03
申请人： Hitoshi Yano , Tomoyuki Yamase , Keiichi Numata , Tadashi Maeda
发明人： Hitoshi Yano , Tomoyuki Yamase , Keiichi Numata , Tadashi Maeda
IPC分类号： H03G3/30
CPC分类号： H03F1/56 , H03F1/02
摘要： The present invention provides an amplifying circuit capable of accomplishing high-impedance input/output, and providing a high gain and low power consumption. The amplifier amplifies a signal received through an input terminal, and outputs the signal through an output terminal. A control circuit comprised of the inductors, and the switches turns input/output impedances of the amplifier into a high impedance.
摘要翻译：本发明提供一种能够实现高阻抗输入/输出并提供高增益和低功耗的放大电路。放大器放大通过输入端接收的信号，并通过输出端输出信号。由电感器组成的控制电路，并且开关将放大器的输入/输出阻抗转换成高阻抗。

32. 发明授权

US6137350A Differential amplifier circuit 有权
标题翻译：差分放大电路
公开(公告)号：US6137350A
公开(公告)日：2000-10-24
申请号：US172861
申请日：1998-10-15
申请人： Tadashi Maeda
发明人： Tadashi Maeda
IPC分类号： H03F3/45 , G06G7/12
CPC分类号： H03F3/45757 , H03F3/45385 , H03F2203/45702
摘要： The average value of an input signal supplied to an input terminal is generated by an integrating circuit consisting of a series circuit of a capacitor, a constant-current source transistor, and a resistor. The average value is used as the reference voltage for the differential amplifier circuit. Further, to each of differential pair transistors the sources of which are commonly connected, other transistors are cascode connected, respectively. Supplied to each gate of the cascode connected transistors is a divisional voltage of the differential voltage between the average voltage from the integrating circuit and the circuit power supply voltage, which divisional voltage is obtained by a capacitive divider circuit.
摘要翻译：通过由电容器，恒流源晶体管和电阻器的串联电路组成的积分电路产生提供给输入端子的输入信号的平均值。平均值用作差分放大器电路的参考电压。此外，对于其源极共同连接的每个差分对晶体管，其他晶体管分别被共源共栅连接。向共源共栅连接的晶体管的每个栅极提供的是积分电路的平均电压与电路电源电压之间的差分电压的分压，该分压是由电容分压电路获得的。

33. 发明授权

US5909128A FETs logic circuit 失效
标题翻译： FET逻辑电路
公开(公告)号：US5909128A
公开(公告)日：1999-06-01
申请号：US823039
申请日：1997-03-21
申请人： Tadashi Maeda
发明人： Tadashi Maeda
IPC分类号： H01L21/8238 , G05F3/24 , H01L27/092 , H03K19/00 , H03K19/0185 , H03K19/0952 , H03K19/094
CPC分类号： H03K19/018535 , G05F3/247 , H03K19/0952
摘要： A semiconductor integrated circuit having a field effect transistor formed on a compound semiconductor is disclosed, that comprises a first power supply, a second power supply for supplying a voltage lower than a voltage that the first power supplies, and at least one virtual power supply that is not connected to the outside and that has a voltage between the voltage of the first power supply and the voltage of the second power supply, wherein the number of the virtual power supplies is designated to a value larger than the quotient of which the voltage between the first power supply and the second power supply is divided by the forward turn-on voltage of a gate electrode of the field effect transistor. In the case that a signal received from a circuit with a low voltage is connected to a circuit between any power supply, the signal is received by a directly coupled logic circuit with a depletion type field effect transistor as a drive circuit. The threshold voltage of the depletion type field effect transistor is -.DELTA.V or higher where .DELTA.V is the voltage between each power supply.
摘要翻译：公开了一种具有形成在化合物半导体上的场效应晶体管的半导体集成电路，其包括第一电源，用于提供低于第一电源供应的电压的第二电源，以及至少一个虚拟电源，没有连接到外部，并且具有第一电源的电压和第二电源的电压之间的电压，其中虚拟电源的数量被指定为大于虚拟电源的数量的值，第一电源和第二电源被场效应晶体管的栅极的正向导通电压除。在从具有低电压的电路接收的信号连接到任何电源之间的电路的情况下，该信号由具有耗尽型场效应晶体管的直接耦合逻辑电路作为驱动电路接收。耗尽型场效应晶体管的阈值电压为△DELTA V或更高，其中DELTA V为每个电源之间的电压。

34. 发明授权

US5696453A GaAs logic circuit with temperature compensation circuitry 失效
标题翻译：具有温度补偿电路的GaAs逻辑电路
公开(公告)号：US5696453A
公开(公告)日：1997-12-09
申请号：US560570
申请日：1995-11-20
申请人： Tadashi Maeda
发明人： Tadashi Maeda
IPC分类号： H03K19/003 , H03K19/0952
CPC分类号： H03K19/00384 , H03K19/0952
摘要： The invention provides a logic circuit including (a) a load element having ends one of which is electrically connected to a first terminal of a voltage source, and the other to an output terminal, (b) a first enhancement mode FET including a drain electrode electrically connected to the output terminal, a gate electrode connected to an input terminal, and a source electrode connected to a junction, (c) a second enhancement mode FET including a drain electrode electrically connected to the first terminal, a gate electrode connected to the output terminal, and a source electrode connected to the junction, and (d) a depletion mode FET including a drain electrode electrically connected to the junction, a gate electrode connected to a control terminal, and a source electrode connected to a second terminal of the voltage source. The logic circuit ensures sufficient noise margin to temperature variation, resulting in a lower supply voltage. In addition, the logic circuit makes it possible to compensate for a variation in logical threshold value of DC transfer characteristic caused by an increase in temperature.
摘要翻译：本发明提供了一种逻辑电路，其包括：（a）负载元件，其端部电连接到电压源的第一端子，另一端连接到输出端子，（b）第一增强型FET，其包括漏电极电连接到输出端子，连接到输入端子的栅极电极和连接到结点的源极电极，（c）包括电连接到第一端子的漏极电极的第二增强模式FET，连接到第一端子的栅电极输出端子和连接到该结点的源电极，以及（d）包含电连接到该结的漏电极的耗尽型FET，连接到控制端子的栅极电极和连接到该控制端子的第二端子的源电极电压源。逻辑电路确保了对温度变化的足够的噪声容限，导致较低的电源电压。此外，逻辑电路使得可以补偿由温度升高引起的DC传递特性的逻辑阈值的变化。

35. 再颁专利

USRE35227E Process and apparatus for analyzing cells 失效
公开(公告)号：USRE35227E
公开(公告)日：1996-05-07
申请号：US198461
申请日：1994-02-17
申请人： Atuo Tomioka , Masayuki Nakagawa , Tadashi Maeda
发明人： Atuo Tomioka , Masayuki Nakagawa , Tadashi Maeda
IPC分类号： G01N15/14 , G01N21/85 , G01N33/48 , G01N33/483 , G01N33/497 , G01N21/05
CPC分类号： G01N15/1404 , G01N2015/1411 , G01N2021/8557 , G01N33/497
摘要： A cell analyzing system flows a liquid to be tested and a sheath liquid through a flattened flow passage. An image of the flattened flow passage is formed at two different magnifications. The thickness of the liquid to be tested in the flattened flow passage is changed between the two different magnifications to maintain this thickness at a value smaller than a depth of field of the apparatus forming the image. The thickness of the liquid to be tested is changed by changing its flow relationship to the sheath liquid.

36. 发明授权

US08248104B2 Phase comparator and phase-locked loop 有权
标题翻译：相位比较器和锁相环
公开(公告)号：US08248104B2
公开(公告)日：2012-08-21
申请号：US12676221
申请日：2008-09-02
申请人： Tadashi Maeda
发明人： Tadashi Maeda
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03K5/26 , H03D13/00 , H03L7/091 , H03L7/093 , H03L2207/50
摘要： A phase comparator is provided that solves the problem that a VCO cannot be controlled with high precision. A frequency divider frequency-divides a VCO signal applied as input to an input terminal (10) in steps, and supplies the VCO signals of each step as output. A latch unit latches the VCO signal that is applied to the input terminal (10) and each VCO signal that was supplied from the frequency divider based on a reference signal that is applied to an input terminal (11). An output unit supplies the latch results realized by the latch unit as phase difference signals that indicate phase differences of the reference signal and the VCO signals.
摘要翻译：提供了一种解决VCO不能以高精度被控制的问题的相位比较器。分频器将逐步施加的输入端的VCO信号分频到输入端子（10），并将每一步的VCO信号作为输出。锁存单元基于施加到输入端子（11）的参考信号，锁存施加到输入端子（10）的VCO信号和从分频器提供的每个VCO信号。输出单元提供由锁存单元实现的锁存结果作为指示参考信号和VCO信号的相位差的相位差信号。

37. 发明授权

US08083121B2 Paste for soldering and soldering method using the same 有权
标题翻译：粘贴焊接和焊接方法使用它
公开(公告)号：US08083121B2
公开(公告)日：2011-12-27
申请号：US10585729
申请日：2005-10-27
申请人： Tadashi Maeda , Tadahiko Sakai
发明人： Tadashi Maeda , Tadahiko Sakai
IPC分类号： B23K31/00
CPC分类号： H05K3/3484 , B23K35/0244 , B23K35/025 , B23K35/282 , B23K35/3006 , B23K35/3013 , B23K35/3613 , H05K3/3436 , H05K3/3463 , H05K3/3489 , H05K2201/0215 , H05K2201/0218 , H05K2201/10992 , Y02P70/613
摘要： In the soldering method, metal-powder-contained flux is disposed between bumps and circuit electrodes when electronic parts are mounted by soldering, the metal powder comprising a core metal formed of metal such as tin and zinc and a surface metal covering surfaces of the core metal formed of noble metal such as gold and silver. Accordingly, metal powder will not remain as residue that is liable to cause migration after the reflow process, and it is possible to assure both soldering effect and insulation effect.
摘要翻译：在焊接方法中，当通过焊接安装电子部件时，在凸起和电路电极之间设置含金属粉末的焊剂，金属粉末包括由诸如锡和锌的金属形成的芯金属和芯的表面金属覆盖表面由贵金属如金和银形成的金属。因此，金属粉末不会残留在回流处理后容易引起迁移的残留物，并且可以确保焊接效果和绝缘效果。

38. 发明申请

US20110121864A1 START SIGNAL DETECTOR CIRCUIT 有权
标题翻译：开始信号检测电路
公开(公告)号：US20110121864A1
公开(公告)日：2011-05-26
申请号：US12095673
申请日：2007-04-05
申请人： Tadashi Maeda , Tomoyuki Yamase
发明人： Tadashi Maeda , Tomoyuki Yamase
IPC分类号： H03K5/153 , H03K3/01 , G05F1/10
CPC分类号： H03D1/10 , F02D2041/0012 , F02D2200/0812 , H03D1/18
摘要： The nonlinearity effect of a rectifying element is enhanced, and further a resonant circuit is used to enlarge the input amplitude. Furthermore, the rectifying efficiency of a detection rectifier circuit is enhanced, thereby allowing the gain of an amplifier circuit in the following stage to be set to a low value. Signals having mutually opposite phases are inputted to RF input terminals (101,102). The signal at the terminal (102) is then inputted to the gate of a transistor (M1) via a capacitor (C3), while the signal at the terminal (101) is then inputted, via a capacitor (C1), to a node (N1) to which the source of the transistor (M1) and the gate and drain of a transistor (M2) are connected, whereby a capacitor (C2) is charged with a half-wave voltage-doubled rectified current. DC biases are inputted to terminals (301,302). There are formed series resonant circuits (L1,C15;L2,C16). A plurality of half-wave voltage-doubled rectifier circuits (M1,M2,C1-C3,R1) are connected in cascade.
摘要翻译：提高了整流元件的非线性效应，并且进一步使用谐振电路来扩大输入幅度。此外，检测整流电路的整流效率提高，从而允许将后续放大器电路的增益设置为低值。具有相互相反相位的信号被输入到RF输入端（101,102）。然后，通过电容器（C3）将端子（102）处的信号输入到晶体管（M1）的栅极，然后通过电容器（C1）将端子（101）处的信号输入到节点（M1）的源极和晶体管（M2）的栅极和漏极连接的晶体管（N1），由此电容器（C2）被充满半波电压倍增的整流电流。 DC偏压被输入到端子（301,302）。形成串联谐振电路（L1，C15; L2，C16）。多个半波倍压整流电路（M1，M2，C1-C3，R1）级联连接。

39. 发明授权

US07816823B2 Cooling device of electric motor for vehicle 有权
标题翻译：车用电动机冷却装置
公开(公告)号：US07816823B2
公开(公告)日：2010-10-19
申请号：US12065040
申请日：2006-04-14
申请人： Hideyuki Yoshizawa , Kazushi Horie , Tadashi Maeda
发明人： Hideyuki Yoshizawa , Kazushi Horie , Tadashi Maeda
IPC分类号： H02K9/02
CPC分类号： H02K9/06
摘要： A cooling device of an electric motor for a vehicle for receiving cooling air into the electric motor through a suction port according to the rotation of a rotor shaft on which a rotor core, which is disposed opposite to a stator core, is installed. The cooling device includes an air volume regulating mechanism regulating a cooling air volume received therein through the suction port according to an ambient temperature. Since the cooling air volume received in the cooling device through the suction port is regulated according to the ambient temperature, the cooling of the electric motor can be optimized, and noise generated can be efficiently reduced according to the ambient temperature.
摘要翻译：一种用于车辆的电动机的冷却装置，其通过吸入口将冷却空气接收到转子轴的旋转中，转子轴上安装有与定子芯相对设置的转子芯。冷却装置包括风量调节机构，其根据环境温度调节通过吸入口容纳在其中的冷却风量。由于通过吸入口容纳在冷却装置中的冷却风量根据环境温度进行调节，所以能够优化电动机的冷却，能够根据环境温度有效地降低产生的噪音。

40. 发明授权

US07663394B2 Start signal detector circuit 有权
标题翻译：启动信号检测电路
公开(公告)号：US07663394B2
公开(公告)日：2010-02-16
申请号：US12162148
申请日：2007-01-11
申请人： Tomoyuki Yamase , Tadashi Maeda
发明人： Tomoyuki Yamase , Tadashi Maeda
IPC分类号： G01R31/26
CPC分类号： H02M7/103 , G01R21/10 , H02M7/217 , H03K17/145 , H03K17/302
摘要： A variation of a threshold of diode-connected transistors is compensated for to maintain a constant rectification efficiency of a rectifier circuit, thereby enabling stable detection of a start signal. A constant voltage is applied to DC bias terminal 103 of cascaded half-wave voltage doubler rectifier circuits (including MOS transistors M1 to M4 and capacitors C1 to C4) forming a rectifier circuit, and a voltage equal to the sum of the constant voltage applied to DC bias terminal 103 and a variation ΔVt of a threshold voltage of the MOS transistors is applied to DC bias terminal 104 of cascaded half-wave voltage doubler rectifier circuits (including MOS transistors M5 to M8 and capacitors C5 to C8) forming a bias circuit.
摘要翻译：二极管连接的晶体管的阈值的变化被补偿以保持整流器电路的恒定的整流效率，从而能够稳定地检测起始信号。将恒定电压施加到形成整流电路的级联半波倍压整流电路（包括MOS晶体管M1至M4和电容器C1至C4）的DC偏置端子103，以及等于施加到直流偏置端子103和MOS晶体管的阈值电压的变化量ΔVt被施加到形成偏置电路的级联半波倍压整流电路（包括MOS晶体管M5至M8和电容器C5至C8）的DC偏置端子104。

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