专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07522455B2 Method and system for reducing soft-writing in a multi-level flash memory 失效
标题翻译：减少多级闪存中软写入的方法和系统
公开(公告)号：US07522455B2
公开(公告)日：2009-04-21
申请号：US11144174
申请日：2005-06-02
申请人： Lorenzo Bedarida , Fabio Tassan Caser , Simone Bartoli , Giorgio Oddone
发明人： Lorenzo Bedarida , Fabio Tassan Caser , Simone Bartoli , Giorgio Oddone
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
摘要翻译：在读取或验证期间减少多级闪存中的软写入的系统和方法包括存储单元。第一和第二参考单元耦合到存储单元，并被配置为接收第一和第二电压。电流比较电路耦合到第一和第二参考单元和存储单元，并且被配置为将通过存储器单元的电流与通过第一和第二参考单元的电流进行比较，并且确定存储器单元是否保持第一在第一参考单元接收到第一电压的同时，如果存储单元不保持第一范围的值，则确定存储单元是否在第二参考单元接收到第二电压时保持第二范围的值，从而在读取操作期间减少软写入。

32. 发明申请

US20080232169A1 NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES 审中-公开
标题翻译： NAND型存储器阵列采用高密度NOR形存储器件
公开(公告)号：US20080232169A1
公开(公告)日：2008-09-25
申请号：US11688740
申请日：2007-03-20
申请人： Massimiliano Frulio , Lorenzo Bedarida , Simone Bartoli , Fabio Tassan Caser
发明人： Massimiliano Frulio , Lorenzo Bedarida , Simone Bartoli , Fabio Tassan Caser
IPC分类号： G11C11/34
CPC分类号： G11C16/08 , G11C5/025 , G11C5/063
摘要： A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality of sub arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines. A local word line driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local word lines in its sub array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bit line driver is coupled between selected ones of the local bit lines in each sub array and selected ones of the plurality of bit lines.
摘要翻译：闪存集成电路包括多个闪存阵列。全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。多个读出放大器分别耦合到多个位线。每个阵列中的多个子阵列每个包括耦合到本地字线和局部位线的多个NAND快闪存储器单元。本地字线驱动器与每个子阵列相关联并且耦合到多个选择线，并且被配置为驱动其子阵列中的与本发明的子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的本地字线中的一个，数组。局部位线驱动器耦合在每个子阵列中的局部位线中的选定的位线和多个位线中的选定的位线之间。

33. 发明授权

US07414891B2 Erase verify method for NAND-type flash memories 有权
标题翻译：擦除NAND型闪存的验证方法
公开(公告)号：US07414891B2
公开(公告)日：2008-08-19
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/00
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

34. 发明申请

US20080170441A1 Sense architecture 有权
标题翻译：感觉架构
公开(公告)号：US20080170441A1
公开(公告)日：2008-07-17
申请号：US11652771
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
发明人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
IPC分类号： G11C16/28
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

35. 发明授权

US07379338B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07379338B2
公开(公告)日：2008-05-27
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

36. 发明授权

US07249215B2 System for configuring parameters for a flash memory 有权
公开(公告)号：US07249215B2
公开(公告)日：2007-07-24
申请号：US11635315
申请日：2006-12-07
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.

37. 发明授权

US06624683B1 Threshold voltage reduction of a transistor connected as a diode 有权
标题翻译：作为二极管连接的晶体管的阈值电压降低
公开(公告)号：US06624683B1
公开(公告)日：2003-09-23
申请号：US09620430
申请日：2000-07-20
申请人： Lorenzo Bedarida , Fabio Disegni , Vincenzo Dima , Simone Bartoli
发明人： Lorenzo Bedarida , Fabio Disegni , Vincenzo Dima , Simone Bartoli
IPC分类号： H03K1704
CPC分类号： H03K17/063 , H03K19/0027
摘要： A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage. 3)
摘要翻译：作为二极管连接的晶体管的电路设计，特别是能够降低晶体管的阈值电压并且等于电路处置中所用晶体管的阈值电压差的设计。电路设计包括具有连接在第一晶体管的栅极和漏极之间的二极管的第二nMOS晶体管的第一pMOS晶体管和连接到两个晶体管的栅极的电流发生器。这种电路设计也适用于nMOS晶体管。从一般观点来看，本发明涉及一种nMOS或pMOS晶体管，其栅极电压（对于nMOS晶体管）增加或减小（对于pMOS晶体管），通过使用与栅极串联的电路，其提供适当的δ 电压。 3）

38. 发明授权

US06480436B2 Non-volatile memory with a charge pump with regulated voltage 有权
标题翻译：具有调节电压的电荷泵的非易失性存储器
公开(公告)号：US06480436B2
公开(公告)日：2002-11-12
申请号：US09909467
申请日：2001-07-19
申请人： Emanuele Confalonieri , Lorenzo Bedarida , Mauro Sali , Simone Bartoli
发明人： Emanuele Confalonieri , Lorenzo Bedarida , Mauro Sali , Simone Bartoli
IPC分类号： G11C700
CPC分类号： G11C16/30
摘要： A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.
摘要翻译：半导体存储器包括彼此连接以形成存储器单元矩阵的多个存储单元。电荷泵连接到存储器单元的矩阵。提供多个可控制的连接元件，每个可控制的连接元件连接在电荷泵的输出端和相应的列线之间。连接到电荷泵的输出端是等效于可控制连接元件的第一元件和等同于预定偏压状态下的存储器单元的第二元件的串联连接。电压调节器连接在第二等效元件和电荷泵的输入端之间，用于基于第二等效元件的端子之间存在的电压来调节其输出电压。

39. 发明授权

US08705283B2 Erase techniques and circuits therefor for non-volatile memory devices 失效
标题翻译：擦除非易失性存储器件的技术和电路
公开(公告)号：US08705283B2
公开(公告)日：2014-04-22
申请号：US13181988
申请日：2011-07-13
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

40. 发明授权

US08599615B2 Memory device in particular extra array configured therein for configuration and redundancy information 失效
标题翻译：存储器件特别地配置在其中用于配置和冗余信息的额外阵列
公开(公告)号：US08599615B2
公开(公告)日：2013-12-03
申请号：US13275708
申请日：2011-10-18
申请人： Simone Bartoli , Mauro Pagliato , Diego Della Mina
发明人： Simone Bartoli , Mauro Pagliato , Diego Della Mina
IPC分类号： G11C11/04 , G11C16/06
CPC分类号： G11C29/789
摘要： Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.
摘要翻译：本文公开了一种装置，其包括多个第一字线，每个第一字线从第一端子中的相关联的一个在第二方向朝向第二端子延伸并且终止于第一和第二端子之间，第二方向基本上垂直于第一方向和多个第二字线，每个第二字线在第三方向上从相关联的一个第二端子延伸到第一端子并且终止于相关联的第一字线之一的端部，第三方向与第一方向相反所述第二方向，所述第二字线中的每一条基本上与所述第一字线中的相关联的一条对齐。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式