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31. 发明申请

US20080246131A1 CHIP PACKAGE STRUCTURE 有权
标题翻译：芯片包装结构
公开(公告)号：US20080246131A1
公开(公告)日：2008-10-09
申请号：US11755753
申请日：2007-05-31
申请人： Yu-Tang Pan , Shih-Wen Chou
发明人： Yu-Tang Pan , Shih-Wen Chou
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/4334 , H01L23/495 , H01L24/31 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48247 , H01L2224/4911 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.
摘要翻译：提供包括电路图案，框架，第一粘合剂层，多个引线，绝缘粘合剂层，芯片，多个第一接合线，多个第二接合线和模制化合物的芯片封装结构。框架和引线设置在电路图案周围。第一粘合层紧固框架和电路图案。绝缘粘合剂层设置在引线和框架之间。芯片具有多个接合焊盘并设置在第一粘合剂层上。第一接合线将接合焊盘分别电连接到电路图案。第二接合线将引线单独地电连接到电路图案。因此，接合焊盘通过第一接合线，电路图案和第二接合线与引线电连接。模塑料覆盖上述组分。

32. 发明申请

US20080017961A1 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：芯片包装结构及其制造方法
公开(公告)号：US20080017961A1
公开(公告)日：2008-01-24
申请号：US11530165
申请日：2006-09-08
申请人： Chun-Hung Lin , Shih-Wen Chou , Yu-Tang Pan
发明人： Chun-Hung Lin , Shih-Wen Chou , Yu-Tang Pan
IPC分类号： H01L21/00
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.
摘要翻译：提供了一种芯片封装结构的制造方法。提供具有第一表面，第二表面和连接第一表面和第二表面的通孔的电路基板。提供具有有源表面的芯片和设置在有源表面上的接合焊盘。芯片固定在电路基板上，其中第二表面与有源表面相对，并且焊盘暴露于通孔。通过通孔形成连接接合焊盘和第一表面的接合线。具有开口的膜形成在第一表面上。接合线，接合焊盘，通孔和第一表面的一部分由开口露出。形成密封剂以封装部分活性表面，接合线和第一表面的一部分。电影被删除。

33. 发明申请

US20070228581A1 UNIVERSAL CHIP PACKAGE STRUCTURE 审中-公开
标题翻译：通用芯片包装结构
公开(公告)号：US20070228581A1
公开(公告)日：2007-10-04
申请号：US11761299
申请日：2007-06-11
申请人： Shih-Wen Chou , Chun-Hung Lin , Wu-Chang Tu , Yu-Tang Pan
发明人： Shih-Wen Chou , Chun-Hung Lin , Wu-Chang Tu , Yu-Tang Pan
IPC分类号： H01L23/52
CPC分类号： H01L23/13 , H01L23/3114 , H01L23/49816 , H01L24/10 , H01L24/45 , H01L24/48 , H01L2224/06135 , H01L2224/06136 , H01L2224/32225 , H01L2224/45144 , H01L2224/4824 , H01L2224/73215 , H01L2224/85186 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.
摘要翻译：提供了包括载体，芯片，多个接合线和模塑料的通用芯片封装结构。载体具有多个通孔，承载表面和对应于承载表面的后表面。后表面具有围绕通孔的多个触点。具有活性表面的芯片和有源表面上的多个接合焊盘设置在承载表面上。活性表面附着在承载表面上，通孔露出接合垫。接合线穿过通孔，以与接合焊盘和触点电连接。此外，可以调整模塑料的形状和尺寸以覆盖芯片，触点和接合线。

34. 发明授权

US06703075B1 Wafer treating method for making adhesive dies 有权
标题翻译：用于制造粘合剂模具的晶片处理方法
公开(公告)号：US06703075B1
公开(公告)日：2004-03-09
申请号：US10327064
申请日：2002-12-24
申请人： Chung-Hung Lin , Jesse Huang , Kuang-Hui Chen , Shih-Wen Chou
发明人： Chung-Hung Lin , Jesse Huang , Kuang-Hui Chen , Shih-Wen Chou
IPC分类号： B05D500
CPC分类号： H01L24/27 , H01L21/6836 , H01L23/3114 , H01L23/3128 , H01L23/4951 , H01L23/49513 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/05599 , H01L2224/06135 , H01L2224/06136 , H01L2224/274 , H01L2224/29101 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/484 , H01L2224/73215 , H01L2224/73265 , H01L2224/83191 , H01L2224/83855 , H01L2224/83856 , H01L2224/85399 , H01L2224/92147 , H01L2225/0651 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.
摘要翻译：提供了一种用于制造粘合剂模具的晶片处理方法。具有两级特性的液体粘合剂涂覆在晶片的表面上。然后，将晶片预固化，使液体粘合剂转变具有玻璃化转变温度不低于40℃的B阶特性的热粘合粘合剂膜，以在室温下无粘合剂进行处理。在定位晶片之后，将晶片单片化以形成具有用于管芯到管芯堆叠，管芯到衬底或管芯到引线框架附接的粘合剂的多个管芯。

35. 发明申请

US20130020688A1 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：芯片包装结构及其制造方法
公开(公告)号：US20130020688A1
公开(公告)日：2013-01-24
申请号：US13479297
申请日：2012-05-24
申请人： Yu-Tang Pan , Shih-Wen Chou
发明人： Yu-Tang Pan , Shih-Wen Chou
IPC分类号： H01L23/495 , H01L21/56
CPC分类号： H01L23/49503 , H01L21/4825 , H01L21/4828 , H01L21/565 , H01L23/3107 , H01L23/49548 , H01L23/49558 , H01L24/73 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/00012
摘要： A chip package structure including a leadframe, a chip, bonding wires and an encapsulant is provided. The leadframe includes a die pad, leads and an insulating layer. The die pad includes a chip mounting portion and a periphery portion. At the periphery portion, the die pad has a second upper surface lying between a first upper surface and a lower surface of the die pad. Each lead includes a suspending portion and a terminal portion. The suspending portion connects to the terminal portion and extends from the terminal portion towards the die pad. The insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad. The chip is disposed on the chip mounting portion. The bonding wires electrically connect the chip to the suspending portions. The encapsulant covers the chip, the bonding wires, the insulating layer, and the leadframe.
摘要翻译：提供包括引线框，芯片，接合线和密封剂的芯片封装结构。引线框架包括管芯焊盘，引线和绝缘层。芯片焊盘包括芯片安装部分和周边部分。在周边部分，管芯焊盘具有位于管芯焊盘的第一上表面和下表面之间的第二上表面。每个引线包括悬挂部分和端子部分。悬挂部分连接到端子部分并且从端子部分朝向芯片焊盘延伸。绝缘层设置在周边部分的第二上表面上，并将悬挂部分连接到管芯焊盘。芯片设置在芯片安装部分上。接合线将芯片电连接到悬挂部分。密封剂覆盖芯片，接合线，绝缘层和引线框架。

36. 发明授权

US08309401B2 Method of manufacturing non-leaded package structure 有权
标题翻译：制造无铅封装结构的方法
公开(公告)号：US08309401B2
公开(公告)日：2012-11-13
申请号：US13030141
申请日：2011-02-18
申请人： Shih-Wen Chou
发明人： Shih-Wen Chou
IPC分类号： H01L21/60
CPC分类号： H01L21/568 , H01L21/4832 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/48465 , H01L2224/49052 , H01L2224/73265 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A manufacturing method of a non-leaded package structure is provided. An upper surface and a lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part and electrically connected to the first protruding parts with a plurality of bonding wires. An encapsulant is formed on the upper surface. A back etching process is performed on the lower surface to partially remove the metal base plate until the encapsulant is exposed and a lead group including at least a die pad and a plurality of leads is defined.
摘要翻译：提供一种非引线封装结构的制造方法。图案化金属基板的上表面和下表面，以在上表面上形成多个第一突出部分和至少第二突出部分，并且在下表面上形成对应于多个第一凹陷图案第一突出部分。第一焊料层分别形成在每个第一凹槽图案中。芯片安装在第二突出部分上并用多个接合线电连接到第一突出部分。在上表面上形成密封剂。在下表面上执行背蚀刻工艺以部分地去除金属基板，直到密封剂暴露，并且限定至少包括管芯焊盘和多个引线的引线组。

37. 发明申请

US20120153449A1 NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非引线包装结构及其制造方法
公开(公告)号：US20120153449A1
公开(公告)日：2012-06-21
申请号：US13030141
申请日：2011-02-18
申请人： Shih-Wen Chou
发明人： Shih-Wen Chou
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L21/568 , H01L21/4832 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/48465 , H01L2224/49052 , H01L2224/73265 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A manufacturing method of a non-leaded package structure is provided. An upper surface and a lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part and electrically connected to the first protruding parts with a plurality of bonding wires. An encapsulant is formed on the upper surface. A back etching process is performed on the lower surface to partially remove the metal base plate until the encapsulant is exposed and a lead group including at least a die pad and a plurality of leads is defined.
摘要翻译：提供一种非引线封装结构的制造方法。图案化金属基板的上表面和下表面，以在上表面上形成多个第一突出部分和至少第二突出部分，并且在下表面上形成对应于多个第一凹陷图案第一突出部分。第一焊料层分别形成在每个第一凹槽图案中。芯片安装在第二突出部分上并用多个接合线电连接到第一突出部分。在上表面上形成密封剂。在下表面上执行背蚀刻工艺以部分地去除金属基板直到密封剂暴露，并且限定包括至少一个管芯焊盘和多个引线的引线组。

38. 发明授权

US08105876B2 Leadframe for leadless package, structure and manufacturing method using the same 有权
公开(公告)号：US08105876B2
公开(公告)日：2012-01-31
申请号：US13016453
申请日：2011-01-28
申请人： Chun Ying Lin , Geng Shin Shen , Yu Tang Pan , Shih Wen Chou
发明人： Chun Ying Lin , Geng Shin Shen , Yu Tang Pan , Shih Wen Chou
IPC分类号： H01L21/00
CPC分类号： H01L21/4842 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/85001 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H05K3/3426 , H05K2201/09745 , H05K2201/10689 , H05K2201/10787 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

39. 发明申请

US20110156281A1 Quad Flat No Lead (QFN) Package 有权
标题翻译：四方扁平无铅（QFN）封装
公开(公告)号：US20110156281A1
公开(公告)日：2011-06-30
申请号：US12832223
申请日：2010-07-08
申请人： Yu-Tang Pan , Shih-Wen Chou
发明人： Yu-Tang Pan , Shih-Wen Chou
IPC分类号： H01L23/49 , H01L23/488
CPC分类号： H01L24/49 , H01L23/3121 , H01L23/49838 , H01L23/49861 , H01L24/29 , H01L24/32 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires. Whereby, the package of the invention can have more inputs/outputs terminals, and the insulating layer can prevent moisture permeation from corroding the joints between the wires and the first pads and the second ends of the traces, thus increasing the reliability of the package of the invention.
摘要翻译：本发明涉及一种四边形无铅（QFN）封装。在本发明中，多个第一焊盘设置在导电电路层的延伸区域的外侧，并且多个第二焊盘设置在导电电路层的管芯接合区域的内部，其中延伸区域围绕管芯接合区域。多个迹线的第一端连接到第二焊盘，并且迹线的第二端位于扩展区域中。绝缘层至少填充芯片接合区域和延伸区域，并且暴露第二焊盘的顶表面和底表面。芯片安装在管芯接合区域，并且多条电线分别将芯片电连接到第一焊盘和迹线的第二端。封装材料用于覆盖导电电路层，芯片和电线。由此，本发明的封装可以具有更多的输入/输出端子，并且绝缘层可以防止水分渗透腐蚀电线与第一焊盘和迹线的第二端之间的接合，从而增加封装的可靠性本发明。

40. 发明授权

US07919874B2 Chip package without core and stacked chip package structure 有权
标题翻译：芯片封装无芯和堆叠芯片封装结构
公开(公告)号：US07919874B2
公开(公告)日：2011-04-05
申请号：US12756377
申请日：2010-04-08
申请人： Yu-Tang Pan , Cheng-Ting Wu , Shih-Wen Chou , Hui-Ping Liu
发明人： Yu-Tang Pan , Cheng-Ting Wu , Shih-Wen Chou , Hui-Ping Liu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/6835 , H01L23/3128 , H01L23/4951 , H01L23/49534 , H01L23/49816 , H01L23/49822 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2221/68345 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
摘要翻译：提供了包括基底，芯片，模塑料和多个外部端子的芯片封装。该基底基本上由具有彼此相对的第一表面和第二表面的图案化电路层和设置在第二表面上的焊接掩模组成，其中该焊接掩模具有多个第一开口，通过该多个第一开口部分图案化电路层被暴露。芯片设置在第一表面上并且电连接到图案化电路层。模塑料覆盖图案电路层并将芯片固定在图案化电路层上。外部端子设置在第一开口中并电连接到图案化电路层。

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