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31. 发明申请

US20120139118A1 SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP FOR REDUCING OPEN FAILURES 有权
标题翻译：半导体芯片，半导体封装和制造半导体芯片的方法，用于减少开路故障
公开(公告)号：US20120139118A1
公开(公告)日：2012-06-07
申请号：US13243575
申请日：2011-09-23
申请人： Seong Cheol KIM
发明人： Seong Cheol KIM
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/0657 , H01L23/481 , H01L2224/16 , H01L2225/06513 , H01L2225/06544
摘要： A semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface, a chip pad disposed on the first surface of the substrate, and a through-silicon via (TSV) including a plurality of sub vias electrically connected to the chip pad at different positions.
摘要翻译：半导体芯片包括具有第一表面和与第一表面相对的第二表面的基板，设置在基板的第一表面上的芯片焊盘以及包括多个子通孔的贯穿硅通孔（TSV），该多个子通孔电连接到芯片垫在不同的位置。

32. 发明申请

US20120061842A1 STACK PACKAGE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：堆叠包装及其制造方法
公开(公告)号：US20120061842A1
公开(公告)日：2012-03-15
申请号：US13228560
申请日：2011-09-09
申请人： Seong Cheol KIM
发明人： Seong Cheol KIM
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/16 , H01L23/3128 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/245 , H01L2224/73204 , H01L2224/73259 , H01L2224/92224 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06548 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15787 , H01L2224/05552 , H01L2924/00
摘要： A stack package includes a substrate, a lower semiconductor chip stacked on the substrate and electrically connected to the substrate through a lower via, a plurality of upper semiconductor chips stacked on the lower semiconductor chip and electrically connected to the lower via through an upper via, wherein the upper semiconductor chips are larger in size than the lower semiconductor chip, and an edge guide electrically connecting edge vias of the upper semiconductor chips and the substrate.
摘要翻译：堆叠封装包括：衬底，堆叠在衬底上的下半导体芯片，并通过下通孔电连接到衬底;堆叠在下半导体芯片上的多个上半导体芯片，并通过上通孔电连接到下通孔; 其中上半导体芯片的尺寸大于下半导体芯片，并且边缘引导件电连接上半导体芯片和衬底的边缘通孔。

33. 发明申请

US20110121462A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权
标题翻译：半导体芯片和半导体封装，包括它们
公开(公告)号：US20110121462A1
公开(公告)日：2011-05-26
申请号：US12835927
申请日：2010-07-14
申请人： Seong Cheol KIM
发明人： Seong Cheol KIM
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L21/563 , H01L23/3128 , H01L23/481 , H01L24/03 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/10126 , H01L2224/13099 , H01L2224/131 , H01L2224/16145 , H01L2224/73203 , H01L2225/06513 , H01L2225/06541 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor chip includes a semiconductor chip body, a through-silicon via and a silicon pattern. The semiconductor chip body has a first surface and a second surface facing away from the first surface. The through-silicon via is formed to pass through the semiconductor chip body and has a metal layer and an insulation layer which protrude from the second surface. The silicon pattern is formed on a sidewall of the protruding through-silicon via.
摘要翻译：半导体芯片包括半导体芯片体，穿硅通孔和硅图案。半导体芯片本体具有第一表面和第二表面，该第二表面背离第一表面。穿通硅通孔被形成为穿过半导体芯片体并且具有从第二表面突出的金属层和绝缘层。硅图案形成在突出的硅通孔的侧壁上。

34. 发明授权

US07898834B2 Semiconductor chip with chip selection structure and stacked semiconductor package having the same 有权
标题翻译：具有芯片选择结构的半导体芯片和具有相同的堆叠半导体封装
公开(公告)号：US07898834B2
公开(公告)日：2011-03-01
申请号：US12059308
申请日：2008-03-31
申请人： Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Ha Na Lee
发明人： Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Ha Na Lee
IPC分类号： G11C5/02
CPC分类号： H01L23/50 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/17 , H01L25/0657 , H01L2224/0235 , H01L2224/02375 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/05552 , H01L2224/06051 , H01L2224/06165 , H01L2224/06167 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/0001 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/00012 , H01L2224/13099
摘要： A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.
摘要翻译：具有适合堆叠半导体芯片的芯片选择结构的半导体芯片包括半导体芯片体和芯片选择结构。芯片选择结构包括设置在半导体芯片主体上的芯片选择焊盘，电连接到芯片选择焊盘的主通孔以及置于主通孔和芯片选择焊盘之间的副通孔。可以通过抵消堆叠的半导体芯片来堆叠各自具有相同芯片选择结构的多个半导体芯片。

35. 发明授权

US07710377B2 LCD panel including gate drivers 有权
标题翻译： LCD面板包括门驱动器
公开(公告)号：US07710377B2
公开(公告)日：2010-05-04
申请号：US11170943
申请日：2005-06-30
申请人： Won-sik Kang , Seong-cheol Kim , Sung-jin Jang , Jae-hyuck Woo , Chul Choi , Kyu-young Chung
发明人： Won-sik Kang , Seong-cheol Kim , Sung-jin Jang , Jae-hyuck Woo , Chul Choi , Kyu-young Chung
IPC分类号： G09G3/36
CPC分类号： G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0224 , G09G2320/0247 , G09G2330/021
摘要： Provided is a liquid crystal display panel having gate drivers. The LCD panel includes a gate line shift circuit setting a gate line scanning order such that the gate lines are sequentially scanned in units of n gate lines with k−1 gate lines between each pair of adjacent gate lines in each unit according to an interleaving method in response to a gate line-on signal received from a timing control unit outside the LCD panel, wherein the LCD panel reproduces source data output from a source driver outside the LCD panel in the gate line scanning order set by the gate line shift circuit. The LCD panel inverts the polarity of a common voltage for every unit of n gate lines, instead of every gate line, thereby reducing power consumption. In addition, since every kth gate line is scanned according to the interleaving method, deterioration of image quality such as a flickering phenomenon can be prevented, which is an advantage of a line inversion driving method.
摘要翻译：具有栅极驱动器的液晶显示面板。 LCD面板包括设置栅线扫描顺序的栅极线移位电路，使得栅极线按照每个单元中每对相邻栅极线之间的k-1条栅极线以n个栅极线为单位依次扫描，根据交错方法响应于从LCD面板外的定时控制单元接收的栅极线路接通信号，其中LCD面板以由栅极线移位电路设置的栅极线扫描顺序从LCD面板外的源极驱动器输出的源数据再现。 LCD面板反转n个栅极线的每个单位的公共电压的极性，而不是每个栅极线，从而降低功耗。此外，由于根据交错方法扫描每个第k个栅极线，因此可以防止诸如闪烁现象的图像质量的劣化，这是线路反转驱动方法的优点。

36. 发明授权

US07595255B2 Method for manufacturing strip level substrate without warpage and method for manufacturing semiconductor package using the same 有权
标题翻译：制造没有翘曲的带状基材的方法以及使用其制造半导体封装的方法
公开(公告)号：US07595255B2
公开(公告)日：2009-09-29
申请号：US11760048
申请日：2007-06-08
申请人： Seong Cheol Kim , Myung Geun Park
发明人： Seong Cheol Kim , Myung Geun Park
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H05K3/0052 , H01L21/561 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/97 , H01L2224/16 , H01L2224/16225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/83 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H05K3/28 , H05K2201/0909 , H05K2201/0989 , H01L2224/85 , H01L2224/81 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate.
摘要翻译：通过以下步骤制造带状平面基板：将阻焊剂涂覆在包含由划线划分的多个单位基板的基板上; 以及对所施加的阻焊剂进行图案化以暴露每个单位基板中的电极端子和球状区域，其中进行阻焊剂的图案化以与施加在划线上的阻焊剂部件一起去除以减少早期翘曲的带状基底。

37. 发明申请

US20090166853A1 MULTI-LAYER STACKED WAFER LEVEL SEMICONDUCTOR PACKAGE MODULE 有权
标题翻译：多层堆叠式水平半导体封装模块
公开(公告)号：US20090166853A1
公开(公告)日：2009-07-02
申请号：US12048304
申请日：2008-03-14
申请人： Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Hyeong Seok Choi , Ha Na Lee
发明人： Sung Min Kim , Chang Jun Park , Kwon Whan Han , Seong Cheol Kim , Hyeong Seok Choi , Ha Na Lee
IPC分类号： H01L23/36
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599
摘要： A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.
摘要翻译：堆叠的晶片级半导体封装模块包括半导体芯片模块，其包括具有矩形形状的第一和第二半导体芯片。第一半导体芯片具有沿其下表面的第一短边设置的第一焊盘。第二半导体芯片具有沿其下表面的第一短边设置的第二焊盘。第一和第二半导体芯片被堆叠以便在叠置的第一和第二半导体芯片的一侧上露出第一焊盘和第二焊盘。封装还包括具有面向第一焊盘的第一连接焊盘和面向第二焊盘的第二连接焊盘的衬底。该包装还包括用于将第一垫连接到第一连接垫的第一连接构件和用于将第二垫连接到第二连接垫的第二连接构件。

38. 发明申请

US20080308949A1 FLIP CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：卷芯片包装及其制造方法
公开(公告)号：US20080308949A1
公开(公告)日：2008-12-18
申请号：US11778253
申请日：2007-07-16
申请人： Seong Cheol KIM , Min Suk SUH
发明人： Seong Cheol KIM , Min Suk SUH
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L24/29 , H01L23/3128 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/83 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/1147 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/16225 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/73204 , H01L2224/838 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/29099 , H01L2224/29199 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit board in a face-down type and having a plurality of bonding pads; conductive polymers for electrically and mechanically connecting the bonding pads of the semiconductor chip and the electrode terminals of the printed circuit board with each other; and an encapsulant for molding one surface of the printed circuit board including the conductive polymers and the semiconductor chip.
摘要翻译：倒装芯片封装实现了细间距并提高了凸块接头的可靠性及其制造方法。倒装芯片封装包括在其一个表面上具有多个电极端子的印刷电路板; 位于印刷电路板上的面朝下型并具有多个接合焊盘的半导体芯片; 用于将半导体芯片的接合焊盘和印刷电路板的电极端子彼此电连接和机械连接的导电聚合物; 以及用于模制包括导电聚合物和半导体芯片的印刷电路板的一个表面的密封剂。

39. 发明授权

US09577948B2 Method and apparatus for connecting to server using trusted IP address of domain 有权
标题翻译：使用域的可信IP地址连接到服务器的方法和装置
公开(公告)号：US09577948B2
公开(公告)日：2017-02-21
申请号：US14122078
申请日：2012-06-01
申请人： Byoung Hoon Kim , Seong Cheol Kim
发明人： Byoung Hoon Kim , Seong Cheol Kim
IPC分类号： G06F15/173 , H04L12/911 , H04L12/24 , H04L29/14 , H04L29/12
CPC分类号： H04L47/70 , H04L41/082 , H04L61/1511 , H04L69/40
摘要： An apparatus for connecting to an update server includes an update unit configured to connect to the update server over a network using a pre-stored domain name address of the update server and an IP address acquisition unit configured to acquire an IP address of the connected update server. The IP address acquired by the IP address acquisition unit is stored as a trusted IP address in a storage unit. The apparatus further includes a reconnection processing unit configured to fetch the trusted IP address of the update server and try connecting to the update server using the trusted IP address in the case of failure to connect to the update server using the pre-stored domain name address.
摘要翻译：用于连接到更新服务器的装置包括：更新单元，被配置为使用预先存储的更新服务器的域名地址通过网络连接到更新服务器;以及IP地址获取单元，被配置为获取所连接的更新的IP地址服务器。由IP地址获取单元获取的IP地址作为可信IP地址存储在存储单元中。该装置还包括：重新连接处理单元，被配置为获取更新服务器的可信IP地址，并且在使用预存的域名地址未能连接到更新服务器的情况下尝试使用可信IP地址连接到更新服务器。

40. 发明申请

US20130045750A1 WIRELESS LOCALIZATION METHOD BASED ON AN EFFICIENT MULTILATERATION ALGORITHM OVER A WIRELESS SENSOR NETWORK AND A RECORDING MEDIUM IN WHICH A PROGRAM FOR THE METHOD IS RECORDED 有权
标题翻译：基于无线传感器网络的有效多路由算法的无线本地化方法和记录方法的程序的记录介质
公开(公告)号：US20130045750A1
公开(公告)日：2013-02-21
申请号：US13337653
申请日：2011-12-27
申请人： Seong Cheol KIM , Jung Kyu LEE
发明人： Seong Cheol KIM , Jung Kyu LEE
IPC分类号： H04W64/00
CPC分类号： G01S5/14 , G01S5/0289 , G01S11/06
摘要： A wireless localization technology using efficient multilateration in a wireless sensor network is disclosed. After calculating estimated distances from each of at least three reference nodes to a blind node using received signal strength of wireless signals that the at least three reference nodes received from the blind node, the estimated location of the blind node is obtained through multilateration using the calculated estimated distances. To correct error in the estimated location, the estimated distances are used, and the error correction direction and error correction distance for the estimated location are calculated by applying a largest weight to the reference node closest to the estimated location. The error of the estimated location is corrected by move the estimated location of the blind node by the calculated error correction direction and error correction distance. Calculation for the error correction is very simple and fast.
摘要翻译：公开了一种在无线传感器网络中使用高效多边测量的无线定位技术。在使用从盲节点接收到的至少三个参考节点的无线信号的接收信号强度来计算从至少三个参考节点中的每一个到盲节点的估计距离之后，通过使用计算出的估计距离为了校正估计位置的误差，使用估计的距离，并且通过对最靠近估计位置的参考节点应用最大权重来计算估计位置的误差校正方向和误差校正距离。通过将计算的误差校正方向和误差校正距离移动盲节点的估计位置来校正估计位置的误差。纠错的计算非常简单快捷。

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