专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06882023B2 Floating resurf LDMOSFET and method of manufacturing same 有权
标题翻译： LDMOSFET浮法晶体管及其制造方法
公开(公告)号：US06882023B2
公开(公告)日：2005-04-19
申请号：US10286169
申请日：2002-10-31
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/1083 , H01L29/42368 , H01L29/66681 , H01L29/7835
摘要： A semiconductor component includes a RESURF transistor (100, 200, 300, 400, 500) that includes a first semiconductor region (110, 210, 310, 410, 510) having a first conductivity type and an electrically-floating semiconductor region (115, 215, 315, 415, 515, 545) having a second conductivity type located above the first semiconductor region. The RESURF transistor further includes a second semiconductor region (120, 220, 320, 420, 520) having the first conductivity type located above the electrically-floating semiconductor region, a third semiconductor region (130, 230) having the first conductivity type located above the second semiconductor region, and a fourth semiconductor region (140, 240, 340, 440, 540) having the second conductivity type located above the second semiconductor region. In a particular embodiment, the fourth semiconductor region and the electrically-floating semiconductor region deplete the second semiconductor region when a reverse bias is applied between the third semiconductor region and the fourth semiconductor region.
摘要翻译：半导体部件包括RESURF晶体管（100,200,300,400,500），其包括具有第一导电类型的第一半导体区域（110,210,310,410,510）和电浮置半导体区域（115， 215,315,415,515,545），其具有位于所述第一半导体区域上方的第二导电类型。 RESURF晶体管还包括具有位于电浮置半导体区域上方的第一导电类型的第二半导体区域（120,220,320,420,520），具有位于上方的第一导电类型的第三半导体区域（130,230）第二半导体区域以及具有位于第二半导体区域上方的第二导电类型的第四半导体区域（140,240,340,440,540）。在特定实施例中，当在第三半导体区域和第四半导体区域之间施加反向偏压时，第四半导体区域和电浮置半导体区域耗尽第二半导体区域。

32. 发明授权

US06703895B1 Semiconductor component and method of operating same 有权
标题翻译：半导体元件及其操作方法
公开(公告)号：US06703895B1
公开(公告)日：2004-03-09
申请号：US10256820
申请日：2002-09-26
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2500
CPC分类号： H01L29/7816 , H01L29/4238 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of a method of redistributing power in a semiconductor component includes varying a saturation current between a drain terminal (330) and a source terminal (320) of a field effect transistor (FET) (200, 500). The FET is at least a portion of the semiconductor component. The threshold voltage of the FET is maintained substantially constant across the FET while the drain-to-source saturation current per unit area is varied across the FET. In one embodiment, the drain-to-source saturation current per unit area is varied such that it is lower at a center of the FET than at a periphery of the FET. In particular embodiments, the drain-to-source saturation current per unit area may be varied across the FET by changing one or more of the gate-to-source voltage, the channel length, the channel width, the gate oxide thickness, and the channel mobility across the FET.
摘要翻译：在半导体部件中重新分配功率的方法的实施例包括改变场效应晶体管（FET）（200,500）的漏极端子（330）和源极端子（320）之间的饱和电流。 FET是半导体部件的至少一部分。 FET的阈值电压在整个FET上保持基本恒定，同时跨FET的每单位面积的漏极 - 源极饱和电流是变化的。在一个实施例中，每单位面积的漏极 - 源极饱和电流是变化的，使得其在FET的中心处比在FET的周边处更低。在特定实施例中，通过改变栅极 - 源极电压，沟道长度，沟道宽度，栅极氧化物厚度和栅极 - 源极电压之间的一个或多个，可以跨FET跨越每单位面积的漏极 - 源极饱和电流 FET上的通道迁移率。

33. 发明授权

US06693339B1 Semiconductor component and method of manufacturing same 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US06693339B1
公开(公告)日：2004-02-17
申请号：US10389401
申请日：2003-03-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2972
CPC分类号： H01L29/7816 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/7835
摘要： A semiconductor component includes a first semiconductor region (110, 210) having a first conductivity type and a second semiconductor region (120, 220) above the first semiconductor region and having a second conductivity type. The semiconductor component further comprises a third semiconductor region (130, 230) above the second semiconductor region and having the first conductivity type, a fourth semiconductor region (140, 240) above the third semiconductor region and having the second conductivity type, a fifth semiconductor region (150, 250) above the third semiconductor region and having the first conductivity type, a sixth semiconductor region (160, 260) substantially enclosed within the fifth semiconductor region and having the second conductivity type, and a seventh semiconductor region (170, 270) above the first semiconductor region and having the second conductivity type. The seventh semiconductor region is adjacent to the third and fourth semiconductor regions, and is separated from the fifth semiconductor region.
摘要翻译：半导体部件包括具有第一导电类型的第一半导体区域（110,210）和位于第一半导体区域上方并且具有第二导电类型的第二半导体区域（120,220）。半导体部件还包括在第二半导体区域上方并具有第一导电类型的第三半导体区域（130,230），在第三半导体区域上方具有第二导电类型的第四半导体区域（140,240），第五半导体区域具有第一导电类型的第一半导体区域（150,250），基本上封装在第五半导体区域内并且具有第二导电类型的第六半导体区域（160,260）和第七半导体区域（170,270）），并且具有第二导电类型。第七半导体区域与第三和第四半导体区域相邻，并且与第五半导体区域分离。

34. 发明授权

US09397233B2 High voltage deep trench capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US09397233B2
公开(公告)日：2016-07-19
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108 , H01L29/94 , H01L27/13 , H01L49/02 , H01L29/66
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

35. 发明授权

US07627428B2 Method of evaluating surface deformation 失效
标题翻译：表面变形评估方法
公开(公告)号：US07627428B2
公开(公告)日：2009-12-01
申请号：US11933862
申请日：2007-11-01
申请人： Ernian Pan , Michael Bevis , Feng Han , Hao Zhou , Ronghua Zhu
发明人： Ernian Pan , Michael Bevis , Feng Han , Hao Zhou , Ronghua Zhu
IPC分类号： G01L1/00
CPC分类号： G01N3/20
摘要： The present invention generally relates to methods for rapidly calculating the surface displacement that results from an arbitrarily shaped load on the surface of a layered substrate. Some embodiments include sparse direct calculations of surface displacement in combination with interpolation methods for estimating surface displacement at other points. Some embodiments include methods for reducing computer time required for calculating surface displacement caused by an arbitrarily shaped load on a layered surface.
摘要翻译：本发明一般涉及快速计算由分层基板的表面上的任意形状的载荷产生的表面位移的方法。一些实施例包括表面位移的稀疏直接计算以及用于估计其他点处的表面位移的插值方法。一些实施例包括用于减少计算由分层表面上的任意形状的载荷引起的表面位移所需的计算机时间的方法。

36. 发明授权

US07439584B2 Structure and method for RESURF LDMOSFET with a current diverter 有权
标题翻译：具有电流分流器的RESURF LDMOSFET的结构和方法
公开(公告)号：US07439584B2
公开(公告)日：2008-10-21
申请号：US11363901
申请日：2006-02-28
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/8611 , H01L29/063 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices. A semiconductor device comprises a semiconductor substrate (22) of a first type; first and second terminals (39,63) laterally spaced-apart on a surface (35) above the substrate; a first semiconductor region (32) of the first type overlying the substrate and ohmically coupled to the first terminal (39); a second semiconductor region (48) of a second opposite type in proximity to the first region and ohmically coupled to the first terminal; a third semiconductor region (30) of the second type overlying the substrate and ohmically coupled to the second terminal (63) and laterally arranged with respect to the first region; a parasitic vertical device comprising the first region and the substrate, the parasitic vertical device for permitting leakage current to flow from the first terminal to the substrate; a fourth semiconductor region (62) of the first type in proximity to the third region and ohmically coupled to the second terminal, thereby forming in combination with the third region a shorted base-collector region of a lateral transistor extending between the first and second terminals to provide diode action; a channel region (27) of the first type separating the first and third regions at the surface; a gate insulator (43) overlying the channel region; and a gate electrode (42) overlying the gate insulator.
摘要翻译：提供了减少RESURF LDMOSFET器件的衬底漏电流的方法和装置。半导体器件包括第一类型的半导体衬底（22）在衬底上方的表面（35）上横向间隔开的第一和第二端子（39,63）第一类型的第一半导体区域（32），覆盖衬底并欧姆耦合到第一端子（39）; 邻近第一区域的第二相对类型的第二半导体区域（48），并且欧姆耦合到第一端子; 第二类型的第三半导体区域（30），覆盖在所述衬底上并且欧姆耦合到所述第二端子（63）并且相对于所述第一区域横向布置; 包括第一区域和衬底的寄生垂直器件，用于允许漏电流从第一端子流到衬底的寄生垂直器件; 第一类型的第四半导体区域（62），邻近第三区域并且欧姆耦合到第二端子，从而与第三区域组合形成在第一和第二端子之间延伸的横向晶体管的短路基极集电极区域提供二极管动作; 所述第一类型的沟道区域（27）在所述表面处分隔所述第一和第三区域; 栅极绝缘体（43），覆盖所述沟道区域; 以及覆盖栅极绝缘体的栅电极（42）。

37. 发明授权

US07405128B1 Dotted channel MOSFET and method 有权
标题翻译：点通道MOSFET及方法
公开(公告)号：US07405128B1
公开(公告)日：2008-07-29
申请号：US11674888
申请日：2007-02-14
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1045 , H01L29/1087 , H01L29/4238 , H01L29/66659 , H01L29/78
摘要： A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.
摘要翻译：改进的MOSFET（50,51,75,215）在半导体本体（56）中具有源极（60）和漏极（62），其被位于源极（56）之间的绝缘控制栅极（66）所覆盖，（60）和漏极（62），并且适于控制在源极（60）和漏极（62）之间延伸的导电通道（55）。绝缘栅极（66）由一系列开口（61）穿孔，通过该开口（61），与体（56）相同导电类型的一系列（例如，正方形）点（69）形式的高度掺杂区域（69）穿过该开口）设置在通道（55）中，彼此间隔开并且与源（60）和排水口（62）间隔开。这些通道点（69）期望地电耦合到主体（56）的高度掺杂的触点（64）。所得到的器件（50,51,75,215）具有比没有点通道的等效现有技术器件（20）更大的SOA，更高的击穿电压和更高的HBM应力电阻。阈值电压不受影响。

38. 发明申请

US20080122025A1 ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STRUCTURE EXTENDING THROUGH A BURIED INSULATING LAYER 有权
标题翻译：电子设备，包括通过绝缘绝缘层延伸的导电结构
公开(公告)号：US20080122025A1
公开(公告)日：2008-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/00
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

39. 发明申请

US20080079122A1 Termination structures for super junction devices 有权
公开(公告)号：US20080079122A1
公开(公告)日：2008-04-03
申请号：US11540770
申请日：2006-09-29
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L23/58
CPC分类号： H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24′ of the second dopant type.

40. 发明授权

US07309638B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US07309638B2
公开(公告)日：2007-12-18
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式