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31. 发明授权

US5123783A Method of reusing slurry 失效
标题翻译：回收浆料的方法
公开(公告)号：US5123783A
公开(公告)日：1992-06-23
申请号：US689053
申请日：1991-06-28
申请人： Hiroshi Yoshida , Takanori Tsutaoka , Toshio Imai , Masahiro Yoshihara , Mitsuhiro Shibazaki , Hiroaki Kubo , Toshitsugu Jinbo , Hiroshi Miyazaki
发明人： Hiroshi Yoshida , Takanori Tsutaoka , Toshio Imai , Masahiro Yoshihara , Mitsuhiro Shibazaki , Hiroaki Kubo , Toshitsugu Jinbo , Hiroshi Miyazaki
IPC分类号： C09K17/04 , E02D3/12 , E21B21/06
CPC分类号： C09K17/04 , E02D3/12 , E21B21/065
摘要： A method of reusing a slurry in a ground improving method, wherein a hardening agent is injected into the ground, and wherein the muddy water (i.e., the slurry which is discharged) upon working is regenerated and again used as an injection material; namely, a hardening agent. By measuring the physical amount indicative of the permeability characteristic of the hardening agent contained in the slurry, an amount of hardening agent contained in the collected slurry (i.e., an amount of hardening agent to be collected) is calculated. Since the amount of collected hardening agent is calculated simultaneously with the collection of the slurry, the amount of hardening agent to be newly injected can be controlled in a real-time manner on the basis of the latest data (i.e., numerical value).
摘要翻译： PCT No.PCT / JP90 / 01100 Sec。 371日期1991年6月28日 102（e）日期1991年6月28日PCT提交1990年8月30日PCT公布。公开号WO91 / 03605 日本1991年3月21日。一种在地面改性方法中再利用浆料的方法，其中将硬化剂注入到地面中，并且其中工作时的泥浆水（即，排出的浆料）被再生并再次使用作为注射材料; 即硬化剂。通过测量指示浆料中所含的硬化剂的渗透特性的物理量，计算收集的浆料中所含的硬化剂的量（即，待收集的硬化剂的量）。由于与收集浆料同时计算收集的固化剂的量，所以可以基于最新数据（即数值）实时地控制新注入的硬化剂的量。

32. 发明授权

US08797807B2 Semiconductor memory and semiconductor memory control method 有权
标题翻译：半导体存储器和半导体存储器控制方法
公开(公告)号：US08797807B2
公开(公告)日：2014-08-05
申请号：US13432708
申请日：2012-03-28
申请人： Masahiro Yoshihara , Katsumi Abe
发明人： Masahiro Yoshihara , Katsumi Abe
IPC分类号： G11C7/10 , G11C16/10 , G11C16/26
CPC分类号： G11C7/1078 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C2207/2227 , G11C2207/2245
摘要： According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，其包括用于存储数据的存储单元，包括锁存器的缓冲电路，每个锁存器包括作为控制元件的晶体管和触发器，以及控制电路，晶体管去激活一个或多个锁存器。

33. 发明授权

US08599613B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08599613B2
公开(公告)日：2013-12-03
申请号：US13428914
申请日：2012-03-23
申请人： Naofumi Abiko , Masahiro Yoshihara
发明人： Naofumi Abiko , Masahiro Yoshihara
IPC分类号： G11C16/00
CPC分类号： G11C16/26 , G11C16/32 , G11C16/3459 , G11C29/702
摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.
摘要翻译：根据一个实施例，非易失性半导体存储器包括存储单元阵列，其包括并行执行读和写的第一单元的存储单元，n（n是不少于2个的自然数）读出放大器，n个检测电路对应配置成将从存储单元阵列读出的第一单位数据分割为z（z为自然数）第二单位数据的累加器，并累加第二单位数据写入不完整的故障位，以及控制电路，被配置为控制在写入之后检测故障位的操作。

34. 发明授权

US08559226B2 Threshold detecting method and verify method of memory cells 有权
标题翻译：存储单元的阈值检测方法和验证方法
公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

35. 发明授权

US08472248B2 Semiconductor memory and control method thereof 有权
标题翻译：半导体存储器及其控制方法
公开(公告)号：US08472248B2
公开(公告)日：2013-06-25
申请号：US13235430
申请日：2011-09-18
申请人： Hiroyuki Kaga , Masahiro Yoshihara , Naofumi Abiko
发明人： Hiroyuki Kaga , Masahiro Yoshihara , Naofumi Abiko
IPC分类号： G11C11/34
CPC分类号： G11C11/4096 , G11C11/5642 , G11C16/0483 , G11C16/08
摘要： According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，存储单元阵列包括存储单元，存储单元沿着行方向和列方向排列，并且分别存储对应于阈值的数据，控制存储器行的行控制电路单元阵列和列控制电路，其包括控制单元，所述控制单元根据与外部地址信号对应的指针，产生对应于存储单元阵列的列的控制元件的信号。

36. 发明申请

US20120250425A1 SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY CONTROL METHOD 有权
标题翻译：半导体存储器和半导体存储器控制方法
公开(公告)号：US20120250425A1
公开(公告)日：2012-10-04
申请号：US13432708
申请日：2012-03-28
申请人： Masahiro YOSHIHARA , Katsumi ABE
发明人： Masahiro YOSHIHARA , Katsumi ABE
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C2207/2227 , G11C2207/2245
摘要： According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，其包括用于存储数据的存储单元，包括锁存器的缓冲电路，每个锁存器包括作为控制元件的晶体管和触发器，以及控制电路，晶体管去激活一个或多个锁存器。

37. 发明申请

US20120250411A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20120250411A1
公开(公告)日：2012-10-04
申请号：US13428914
申请日：2012-03-23
申请人： Naofumi ABIKO , Masahiro Yoshihara
发明人： Naofumi ABIKO , Masahiro Yoshihara
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/32 , G11C16/3459 , G11C29/702
摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.
摘要翻译：根据一个实施例，非易失性半导体存储器包括存储单元阵列，其包括并行执行读和写的第一单元的存储单元，n（n是不少于2个的自然数）读出放大器，n个检测电路对应配置成将从存储单元阵列读出的第一单位数据分割为z（z为自然数）第二单位数据的累加器，并累加第二单位数据写入不完整的故障位，以及控制电路，被配置为控制在写入之后检测故障位的操作。

38. 发明申请

US20110305089A1 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS 有权
标题翻译：记忆细胞的阈值检测方法和验证方法
公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/34 , G11C16/26 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

39. 发明授权

US07839679B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07839679B2
公开(公告)日：2010-11-23
申请号：US12043510
申请日：2008-03-06
申请人： Koji Hosono , Masahiro Yoshihara , Dai Nakamura , Youichi Kai
发明人： Koji Hosono , Masahiro Yoshihara , Dai Nakamura , Youichi Kai
IPC分类号： G11C16/06 , G11C5/14
CPC分类号： G11C16/30 , G11C5/14 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers.
摘要翻译：根据本发明的一个方面的非易失性半导体存储器包括存储单元阵列，其包括多个单元单元，设置在存储单元阵列的第一方向上的一端的电源垫，以及设置在存储单元的第一方向上的页缓冲器阵列非易失性半导体存储器还包括多个位线，它们沿着第一方向延伸设置在存储单元阵列上，第一电源线设置在存储单元阵列上的多个位线上，以将电源焊盘和页面缓冲区。

40. 发明申请

US20090161436A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090161436A1
公开(公告)日：2009-06-25
申请号：US12335093
申请日：2008-12-15
申请人： Naofumi Abiko , Masahiro Yoshihara
发明人： Naofumi Abiko , Masahiro Yoshihara
IPC分类号： G11C16/04 , G11C16/06 , G11C5/14
CPC分类号： G11C16/0483 , G11C5/147 , G11C8/10 , G11C16/26 , G11C16/30
摘要： The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state.
摘要翻译：与本发明的实施例相关的半导体存储器件包括连接有多个存储单元的存储器串，连接到存储器串的端部的位线，产生电压或电流相关的电源电路提供每个存储单元的操作状态，根据在电源电路中产生的电压或电流，通过位线提供控制电压或控制电流的读出放大器，其控制每个存储单元的操作状态，以及瞬态响应调整电路，当感测放大器向位线提供控制电压或将存储器串从第一操作状态转移到第二操作状态的控制电流时，调整在电源电路中产生的电压或电流的瞬态响应特性操作状态

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