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31. 发明申请

US20090187716A1 Network On Chip that Maintains Cache Coherency with Invalidate Commands 失效
标题翻译：使用无效命令保持缓存一致性的片上网络
公开(公告)号：US20090187716A1
公开(公告)日：2009-07-23
申请号：US12015975
申请日：2008-01-17
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) that maintains cache coherency, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, at least one memory communications controller further comprising a cache coherency controller each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译：一种保持高速缓存一致性的网络芯片（NOC），NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器适应于路由器，网络接口控制器，至少一个存储器通信控制器，其还包括高速缓存一致性控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，其中所述存储器通信控制器被配置执行存储器访问指令并被配置为确定由存储器访问指令寻址的高速缓存行的状态，高速缓存行的状态是共享的，排他的或无效的之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。

32. 发明申请

US20090182944A1 Processing Unit Incorporating L1 Cache Bypass 失效
标题翻译：结合L1缓存旁路的处理单元
公开(公告)号：US20090182944A1
公开(公告)日：2009-07-16
申请号：US11972221
申请日：2008-01-10
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0811
摘要： A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
摘要翻译：在将所请求的数据返回到请求者的同时，在将所请求的数据缓存在较低级别的高速缓存中的同时，电路装置和方法将所请求的数据的存储绕过多层存储器体系结构的更高级缓存。对于某些类型的数据，例如仅使用一次和/或很少被修改或写回存储器的数据，绕过较高级别高速缓存中的存储降低了请求的数据从较高级别投出常用数据的可能性缓存。然而，通过将数据缓存在较低级别的缓存中，低级缓存仍然可以窥探数据请求，并在数据已经缓存在较低级别缓存中的情况下返回请求的数据。

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