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31. 发明申请

US20130328592A1 TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC 失效
标题翻译：时分多路复用有限公司开关动态逻辑
公开(公告)号：US20130328592A1
公开(公告)日：2013-12-12
申请号：US13524562
申请日：2012-06-15
申请人： LELAND CHANG , ROBERT K. MONTOYE , YUTAKA NAKAMURA
发明人： LELAND CHANG , ROBERT K. MONTOYE , YUTAKA NAKAMURA
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/096
摘要： A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.
摘要翻译：一种用于在有限交换机动态逻辑（LSDL）电路中提高性能的方法包括在第一和第二评估时钟信号的预充电阶段期间对动态节点进行预充电。在第一评估时钟信号的评估阶段响应于第一评估树的一个或多个第一输入信号，将动态节点评估为第一逻辑值。在第二评估时钟信号的评估阶段期间响应于第二评估树的一个或多个第二输入信号，将动态节点评估为第二逻辑值。响应于动态节点根据输出锁存时钟信号输出LSDL电路的信号。

32. 发明授权

US08605499B2 Resonance nanoelectromechanical systems 有权
标题翻译：共振纳米机电系统
公开(公告)号：US08605499B2
公开(公告)日：2013-12-10
申请号：US13092247
申请日：2011-04-22
申请人： Leland Chang , Michael A. Guillorn , Dechao Guo , Fei Liu , Keith Kwong Hon Wong
发明人： Leland Chang , Michael A. Guillorn , Dechao Guo , Fei Liu , Keith Kwong Hon Wong
IPC分类号： G11C11/50
CPC分类号： H03H9/2457 , G11C11/404 , G11C23/00 , H03H2009/02314
摘要： Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions.
摘要翻译：用栅电极操作纳米级悬臂梁的系统和方法。示例性系统包括耦合到栅电极的驱动电路，其中来自电路的驱动信号可以使光束在光束的共振频率处或其附近振荡。驱动信号包括AC分量，并且还可以包括DC分量。替代示例系统包括纳米级悬臂梁，其中光束振荡以接触多个漏极区域。

33. 发明授权

US08580624B2 Nanowire FET and finFET hybrid technology 失效
标题翻译：纳米线FET和finFET混合技术
公开(公告)号：US08580624B2
公开(公告)日：2013-11-12
申请号：US13286311
申请日：2011-11-01
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/1211 , B82Y10/00 , B82Y40/00 , H01L21/3247 , H01L21/845 , H01L29/0673 , H01L29/42392 , H01L29/66469 , H01L29/78696
摘要： Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.
摘要翻译：提供了混合纳米线FET和FinFET器件及其制造方法。一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。提供了在BOX上具有活性层的晶片。有源层的第一区域变薄。有机平面化层沉积在有源层上。使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。使用第二硬掩模在活性层的第二区域中蚀刻金箔。形成围绕每个纳米线的至少一部分的第一栅极堆叠。形成第二栅极堆叠，覆盖每个散热片的至少一部分。在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

34. 发明授权

US08536041B2 Method for fabricating transistor with high-K dielectric sidewall spacer 有权
标题翻译：用于制造具有高K电介质侧壁间隔物的晶体管的方法
公开(公告)号：US08536041B2
公开(公告)日：2013-09-17
申请号：US13559182
申请日：2012-07-26
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L27/01
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823462 , H01L21/823468 , H01L21/823807 , H01L21/823857 , H01L21/823864 , H01L27/1203 , H01L29/4958 , H01L29/517 , H01L29/66772 , H01L29/78654
摘要： A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.
摘要翻译：提供了一种用于制造晶体管的方法。该晶体管包括一个硅层，该硅层包括一个源区和一个漏极区，一个位于源极区和漏极区之间的硅层上的栅极堆叠，以及设置在栅叠层的侧壁上的侧壁隔离层。栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。还提供了制造这种晶体管的方法。

35. 发明授权

US08493093B1 Time division multiplexed limited switch dynamic logic 失效
公开(公告)号：US08493093B1
公开(公告)日：2013-07-23
申请号：US13494607
申请日：2012-06-12
申请人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： H03K19/00
CPC分类号： H03K19/0963 , H03K19/096
摘要： A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

36. 发明申请

US20130176771A1 8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES 有权
标题翻译：具有外部门极二极管的8晶体管SRAM单元设计
公开(公告)号：US20130176771A1
公开(公告)日：2013-07-11
申请号：US13345636
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C16/24 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译：一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

37. 发明申请

US20130153996A1 HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE 有权
标题翻译： HYBRID CMOS NANOWIRE MESH DEVICE和PDSOI DEVICE
公开(公告)号：US20130153996A1
公开(公告)日：2013-06-20
申请号：US13328069
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/088 , H01L21/28 , H01L29/78 , B82Y40/00 , B82Y99/00
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和PDSOI器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和PDSOI器件的半导体结构。

38. 发明申请

US20130087882A1 LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION 有权
公开(公告)号：US20130087882A1
公开(公告)日：2013-04-11
申请号：US13269552
申请日：2011-10-07
申请人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
发明人： Josephine B. Chang , Leland Chang , Sebastian U. Engelmann , Michael A. Guillorn
IPC分类号： H01L27/12 , H01L21/56
CPC分类号： B81C1/0023 , B81B2207/015 , B81C1/00801 , B81C2203/0714 , B81C2203/0742 , H01L21/565 , H01L21/845 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

39. 发明申请

US20130026449A1 Hybrid CMOS Technology with Nanowire Devices and Double Gated Planar Devices 失效
标题翻译：混合CMOS技术与纳米线器件和双门控平面器件
公开(公告)号：US20130026449A1
公开(公告)日：2013-01-31
申请号：US13189999
申请日：2011-07-25
申请人： Sarunya BANGSARUNTIP , Josephine B. CHANG , Leland CHANG , Jeffrey W. SLEIGHT
发明人： Sarunya BANGSARUNTIP , Josephine B. CHANG , Leland CHANG , Jeffrey W. SLEIGHT
IPC分类号： H01L29/775 , H01L21/336 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/045 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/513 , H01L29/66439 , H01L29/66772 , H01L29/78648 , H01L29/78696
摘要： A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.
摘要翻译：衬底包括第一源极区域和第一漏极区域，每个第一漏极区域具有设置在第二半导体层上的第一半导体层和平行于{110}晶面的平面和平行于{110}晶面的相对侧壁表面的表面; 纳米线通道部件由第一源极区域和第一漏极区域悬挂，其中纳米线通道构件包括第一半导体层，以及平行于{100}晶面的相对侧壁表面和平行于{110}晶面的相对面。衬底还包括具有第一源极和漏极区域的特性的第二源极和漏极区域以及由第二源极区域和第二漏极区域悬置并且具有与纳米线通道构件相同的特性的单个沟道构件。单通道构件的宽度是单个纳米线构件的宽度的至少几倍。

40. 发明授权

US08304837B2 Differentially recessed contacts for multi-gate transistor of SRAM cell 有权
标题翻译： SRAM单元的多栅极晶体管的差分凹陷触点
公开(公告)号：US08304837B2
公开(公告)日：2012-11-06
申请号：US12816825
申请日：2010-06-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/70
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A complementary metal-oxide-semiconductor static random access memory cell that includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount.
摘要翻译：具有多个P沟道多栅极晶体管和多个N沟道多栅极晶体管的互补金属氧化物半导体静态随机存取存储单元。每个晶体管包括栅电极和由至少一个栅极电极隔开的源极和漏极区域。 SRAM单元还包括形成在至少一个晶体管的源区和漏区内的多个触点。至少一个晶体管的多个触点凹入预定的凹陷量，其中至少一个晶体管的电阻基于预定的凹陷量而变化。

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