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31. 发明申请

US20090327792A1 BUS FREQUENCY ADJUSTMENT CIRCUITRY FOR USE IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE 有权
标题翻译：总线频率调整电路用于动态随机访问存储器件
公开(公告)号：US20090327792A1
公开(公告)日：2009-12-31
申请号：US12163663
申请日：2008-06-27
申请人： Joe Salmon , Kuljit Bains
发明人： Joe Salmon , Kuljit Bains
IPC分类号： G06F1/06
CPC分类号： G06F1/10 , G06F1/06
摘要： The present disclosure relates to clock divider circuitry for use in a dynamic random access memory device. In accordance with at least one embodiment the disclosure includes a method having a number of operations. Some operations may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving said clock input signal and said output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving said multiplexed output at a first bus configured to receive said multiplexed output and to reduce an operational frequency of said first bus in response to an increase in an operational frequency of a second bus associated with said memory device.
摘要翻译：本公开涉及用于动态随机存取存储器件的时钟分配器电路。根据至少一个实施例，本公开包括具有多个操作的方法。一些操作可以包括在时钟分频器电路处从时钟输入接收器接收具有第一频率的时钟输入信号，时钟分频器电路包括被配置为产生输出信号的触发器，至少部分地基于反相输出信号和时钟输入信号。输出信号可以具有第二频率，其是第一频率的一部分。该方法还可以包括在多路复用器处接收所述时钟输入信号和所述输出信号，并产生多路复用输出。该方法可以另外包括在被配置为接收所述多路复用输出的第一总线处接收所述多路复用输出并且响应于与所述存储器件相关联的第二总线的工作频率的增加而减小所述第一总线的工作频率。

32. 发明申请

US20070121399A1 Semiconductor memory devices and systems, and methods of using having reduced timers and registers 有权
标题翻译：半导体存储器件和系统以及使用方法具有减少的定时器和寄存器
公开(公告)号：US20070121399A1
公开(公告)日：2007-05-31
申请号：US11291285
申请日：2005-11-30
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22
摘要： A device including a command decoder to receive a compound command, a timer to begin operating if the compound command includes an activate command and a precharge command, the timer to begin operating at substantially the same time as the activate command is issued, and control logic coupled to the command decoder to precharge bit lines no earlier than when the timer reaches a target time period.
摘要翻译：一种装置，包括用于接收复合命令的命令解码器，如果所述复合命令包括激活命令和预充电命令，定时器开始运行，所述定时器开始在与所述激活命令相同的时间开始操作，以及控制逻辑耦合到命令解码器，以便在定时器达到目标时间段之前不对其进行预充电。

33. 发明申请

US20070005826A1 Termination control in memory systems 审中-公开
标题翻译：内存系统中的终止控制
公开(公告)号：US20070005826A1
公开(公告)日：2007-01-04
申请号：US11171624
申请日：2005-06-30
申请人： Hsien-Pao Yang , Kuljit Bains , Ron Starbuck
发明人： Hsien-Pao Yang , Kuljit Bains , Ron Starbuck
IPC分类号： G06F13/28
CPC分类号： G06F13/1684 , G11C5/063
摘要： A memory controller includes controllable on-die terminations that may be turned on and off separately.
摘要翻译：存储器控制器包括可以单独打开和关闭的可控的管芯端子。

34. 发明申请

US20060004981A1 Apparatus and method for initialization of a double-sided dimm having at least one pair of mirrored pins 有权
标题翻译：用于初始化具有至少一对镜像引脚的双面dimm的装置和方法
公开(公告)号：US20060004981A1
公开(公告)日：2006-01-05
申请号：US10881452
申请日：2004-06-30
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G11C7/1045
摘要： A method and apparatus for initialization of a double-sided memory module having a least one pair of mirrored pins. In one embodiment, the method includes the generation of an opcode to initialize a first side of the memory module according to a first side pin routing. In one embodiment, the opcode is written to a host address selected for the first side of the memory module according to a system host address to memory address mapping. In one embodiment, the opcode is altered if a routing of address pins of the opposed side of the memory module are interchanged with reference to the first side pin routing. Subsequently, a unique host address is selected to produce the altered opcode at the address pins of the opposed side of the memory module according to a defined host address to memory address mapping. Other embodiments are described and claimed.
摘要翻译：一种用于初始化具有至少一对镜像引脚的双面存储器模块的方法和装置。在一个实施例中，该方法包括生成操作码以根据第一侧引脚布线来初始化存储器模块的第一侧。在一个实施例中，根据系统主机地址到存储器地址映射，将操作码写入到为存储器模块的第一侧选择的主机地址。在一个实施例中，如果存储器模块的相对侧的地址引脚的布线参考第一侧引脚布线互换，则操作码被改变。随后，根据定义的主机地址到存储器地址映射，选择唯一的主机地址以在存储器模块的相对侧的地址引脚处产生改变的操作码。描述和要求保护其他实施例。

35. 发明申请

US20050144375A1 Method and apparatus to counter mismatched burst lengths 有权
标题翻译：用于计算不匹配突发长度的方法和装置
公开(公告)号：US20050144375A1
公开(公告)日：2005-06-30
申请号：US10750154
申请日：2003-12-31
申请人： Kuljit Bains , John Halbert , Randy Osborne
发明人： Kuljit Bains , John Halbert , Randy Osborne
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/161
摘要： Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.
摘要翻译：具有存储单元组的存储器单元被组织成共享控制电路的两组存储体，以及数据缓冲器以提供与存储器总线的接口，但它们独立地可操作以足以支持与每个组的无关交易，并且可以用于交错以缩短的突发传输进行读操作，以最大限度地减少内存总线上的死区时间。

36. 发明授权

US6154825A Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations 失效
标题翻译：用于寻址包括具有多种配置的存储器设备的存储器资源的方法和装置
公开(公告)号：US6154825A
公开(公告)日：2000-11-28
申请号：US814733
申请日：1997-03-07
申请人： Robert N. Murdoch , Michael W. Williams , Kuljit Bains , Narendra Khandekar
发明人： Robert N. Murdoch , Michael W. Williams , Kuljit Bains , Narendra Khandekar
IPC分类号： G06F12/02 , G06F12/06 , G06F12/10
CPC分类号： G06F12/06 , G06F12/0215
摘要： A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle. A row address is then generated by selecting predetermined bits of the memory address as the row address. Concurrently with the generation of the row address, a determination is made as to the configuration of a memory device within the memory resource and targeted by the memory address. Thereafter, a column address is generated by selecting bits of the memory address as the column address based on the configuration of the targeted memory device. The time required for the determination of the configuration of the targeted memory device is thus absorbed within the time expended generating the row address.
摘要翻译：描述了用于访问诸如DRAM模块阵列之类的存储器资源的方法和装置。该方法开始于在存储器访问周期期间接收到存储器地址。然后通过选择存储器地址的预定位作为行地址来生成行地址。与行地址的产生同时，确定存储器资源内的存储器设备的配置并且由存储器地址对准。此后，基于目标存储器件的配置，通过选择存储器地址的位作为列地址来生成列地址。因此，确定目标存储器件的配置所需的时间在生成行地址的时间内被吸收。

37. 发明授权

US5815167A Method and apparatus for providing concurrent access by a plurality of agents to a shared memory 失效
标题翻译：用于提供由多个代理程序并发访问共享存储器的方法和装置
公开(公告)号：US5815167A
公开(公告)日：1998-09-29
申请号：US672099
申请日：1996-06-27
申请人： Manish Muthal , Nilesh V. Shah , Kuljit Bains
发明人： Manish Muthal , Nilesh V. Shah , Kuljit Bains
IPC分类号： G06T1/60 , G06F12/06 , G06F13/16 , G06F13/18 , G06F15/16 , G06F15/167 , G06T1/20 , G09G5/00
CPC分类号： G06F15/167 , G06F13/1647
摘要： A computer system, including a graphics controller and a memory controller, employs a Shared Frame Buffer Architecture, and accordingly has a shared memory in the form a bank of DRAMs. The shared memory is accessible by both the memory and graphics controllers. The memory includes a shared DRAM row in which a Shared Frame Buffer (SFB) aperture is defined. An interface selectively provides access to the shared DRAM row by the graphics or memory controller, while providing permanent access to the remaining DRAM rows by the memory controller. This facilitates concurrent access by the graphics controller and the memory controller to the shared DRAM row and to the remaining DRAM rows respectively, in a first memory access scenario. The accessibility of the shared DRAM row by the memory controller, in a second memory access scenario, is also maintained. The interface includes a selector circuit, such as a multiplexor or Q-switch, coupled to receive memory address signals and control signals from the graphics controller and the memory controller via a dedicated bus from each of these controllers. The selector circuit is operable selectively to present either memory address to the shared DRAM row, in which the SFB aperture is defined, and also selectively to provide access to the shared DRAM row by either controller. The selector circuit is operable by a logic circuit, incorporated within the systems controller, which determines whether a memory access request received from the memory controller is to an address in the shared DRAM row, or in the remaining DRAM rows.
摘要翻译：包括图形控制器和存储器控制器的计算机系统采用共享帧缓冲器架构，因此具有一组DRAM形式的共享存储器。共享内存可由内存和图形控制器访问。存储器包括共享DRAM行，其中定义了共享帧缓冲器（SFB）孔径。接口选择性地提供对图形或存储器控制器对共享DRAM行的访问，同时由存储器控制器永久地访问剩余的DRAM行。这有助于在第一存储器访问场景中分别由图形控制器和存储器控制器同时访问共享的DRAM行和剩余的DRAM行。在第二存储器访问场景中，存储器控制器的共享DRAM行的可访问性也被保持。该接口包括诸如多路复用器或Q开关的选择器电路，其经由来自这些控制器中的每一个的专用总线耦合以从图形控制器和存储器控制器接收存储器地址信号和控制信号。选择器电路可选择地可操作地将存储器地址呈现给共享DRAM行，其中定义了SFB孔径，并且还选择性地通过任一控制器提供对共享DRAM行的访问。选择器电路可由逻辑电路操作，该逻辑电路包括在系统控制器内，该逻辑电路确定从存储器控制器接收到的存储器访问请求是否是共享DRAM行中的地址或剩余的DRAM行中的地址。

38. 发明授权

US5802603A Method and apparatus for asymmetric/symmetric DRAM detection 失效
标题翻译：用于非对称/对称DRAM检测的方法和装置
公开(公告)号：US5802603A
公开(公告)日：1998-09-01
申请号：US599056
申请日：1996-02-09
申请人： Kuljit Bains , Narendra Khandekar
发明人： Kuljit Bains , Narendra Khandekar
IPC分类号： G06F12/06 , G11C29/10 , G11C29/36 , G06F12/02
CPC分类号： G06F12/0684 , G11C29/10 , G11C29/36
摘要： A method and apparatus for detecting DRAM symmetry. A memory address including a row address and a column address bit is forced to a known value regardless of the host bit which would otherwise be mapped thereto. If the forced bit is in the column address it should be a bit which is not used by an asymmetric DRAM of the depth in the system to be tested, but would be used in a symmetric DRAM of the same depth. Conversely, if the forced bit is in the row address the bit should be used in the asymmetric case but not in the symmetric case. It is important that regardless of what bit in the memory address is forced, the forced bit should not be used by both cases at the depth tested. A first and second known value, are written respectively to two memory addresses which differ only in the value which would normally be mapped to this forced bit. The forced bit will cause an overwrite if the DRAM is of the type which uses the forced bit in its addressing. Thus, by reading the potentially overwritten address, symmetry is determined.
摘要翻译：一种用于检测DRAM对称性的方法和装置。包括行地址和列地址位的存储器地址被强制为已知值，而不管否则将映射到其的主机位。如果强制位在列地址中，那么它应该是一个不被被测系统深度的非对称DRAM使用的位，但是将被用在相同深度的对称DRAM中。相反，如果强制位在行地址中，那么该位应在非对称情况下使用，但不在对称情况下使用。重要的是，无论内存地址中的哪一位被强制，强制位不应该在被测深度的情况下使用。第一和第二已知值被分别写入两个存储器地址，这两个存储器地址仅在通常被映射到该强制位的值上不同。如果DRAM是在其寻址中使用强制位的类型，则强制位将导致覆盖。因此，通过读取可能覆盖的地址，确定对称性。

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