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31. 发明授权

US5434098A Double poly process with independently adjustable interpoly dielectric thickness 失效
标题翻译：双聚合工艺，具有独立可调的叠层电介质厚度
公开(公告)号：US5434098A
公开(公告)日：1995-07-18
申请号：US253327
申请日：1994-06-03
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： H01L21/02 , H01L21/822 , H01L21/8238
CPC分类号： H01L28/40 , H01L21/8221 , Y10S438/981
摘要： The present invention relates to a double poly MOS structure and a method for polysilicon capacitor formation which allows for independent adjustment of an interpoly oxide layer without affecting thickness of the gate oxide layer. In an exemplary embodiment, a first oxide layer is formed above a polysilicon layer. A second oxide layer is subsequently formed on the substrate to establish a gate oxide in an active area of the transistor. As a result, the interpoly oxide layer is formed by a combination of the first and second oxide formations, while the gate oxide layer is formed by only the second oxide formation. Thus, the thickness of the interpoly oxide layer can be adjusted by increasing or decreasing the thickness of the first oxide formation without changing the thickness of the gate oxide layer.
摘要翻译：本发明涉及双多晶硅结构和多晶硅电容器形成方法，其允许独立调整多晶硅氧化物层而不影响栅极氧化物层的厚度。在示例性实施例中，在多晶硅层上方形成第一氧化物层。随后在衬底上形成第二氧化物层以在晶体管的有效区域中建立栅极氧化物。结果，通过第一氧化物层和第二氧化物层的组合形成多晶硅氧化物层，而栅极氧化层仅通过第二氧化物形成而形成。因此，可以通过增加或减小第一氧化物形成的厚度而不改变栅极氧化物层的厚度来调节多晶硅氧化物层的厚度。

32. 发明授权

US08034712B2 Method of fabricating dual damascene structure 有权
标题翻译：双镶嵌结构的制作方法
公开(公告)号：US08034712B2
公开(公告)日：2011-10-11
申请号：US12897073
申请日：2010-10-04
申请人： Kuang-Yeh Chang , Hong Ma
发明人： Kuang-Yeh Chang , Hong Ma
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144
摘要： A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed.
摘要翻译：描述了制造双镶嵌结构的方法。介电层和金属硬掩模层依次形成在其上具有导电层和衬垫层的基板上。将金属硬掩模层和电介质层图案化以形成露出衬垫层的一部分的通孔。通孔中填充间隙填充层，其高度为通孔深度的1/4至1/2。在金属硬掩模层和电介质层中形成沟槽。去除间隙填充层以露出衬里层的部分，然后将其移除。形成填充在通孔和沟槽中的金属层，然后去除金属硬掩模层。

33. 发明授权

US07030952B2 Microdisplay pixel cell and method of making it 失效
公开(公告)号：US07030952B2
公开(公告)日：2006-04-18
申请号：US09683364
申请日：2001-12-19
申请人： Kuang-Yeh Chang , Kuo-Yun Kuo
发明人： Kuang-Yeh Chang , Kuo-Yun Kuo
IPC分类号： G02F1/1343
CPC分类号： G02F1/136 , G02F1/136277
摘要： A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.

34. 发明授权

US06835584B2 Microdisplay pixel cell and method of making it 失效
标题翻译：微显示像素单元及其制作方法
公开(公告)号：US06835584B2
公开(公告)日：2004-12-28
申请号：US10605897
申请日：2003-11-05
申请人： Kuang-Yeh Chang , Kuo-Yun Kuo
发明人： Kuang-Yeh Chang , Kuo-Yun Kuo
IPC分类号： H01L2100
CPC分类号： G02F1/136 , G02F1/136277
摘要： A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.
摘要翻译：多个有源区域被限定在半导体衬底上。然后在半导体衬底上形成至少一个栅极以覆盖有源区的一部分。此后，在未被栅极覆盖的有源区域中形成多个源极/漏极，随后在半导体衬底上形成覆盖栅极和源极/漏极的第一电介质层。之后，在第一电介质层的顶部形成至少一个像素盖顶板，并且在顶板的表面顶部形成电容器电介质层。最后，至少一个像素帽底板形成在第一介电层的顶部以覆盖顶板。

35. 发明授权

US06228703B1 Method of fabricating mixed-mode semiconductor device having a capacitor and a gate 有权
标题翻译：制造具有电容器和栅极的混合模式半导体器件的方法
公开(公告)号：US06228703B1
公开(公告)日：2001-05-08
申请号：US09209648
申请日：1998-12-10
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： H01L218242
CPC分类号： H01L27/0629 , H01L28/40
摘要： A method of fabricating a mixed mode semiconductor device. A semiconductor substrate having a device isolation region and a gate oxide layer formed thereon is provided. A first conductive layer is formed to cover the device isolation region and the gate oxide layer. A dielectric layer if formed over the device isolation region to cover a part of the first conductive layer. A second conductive layer is formed on the dielectric layer and the first conductive layer. The second conductive layer and the first conductive layer are patterned to form a capacitor and a gate.
摘要翻译：一种制造混合模式半导体器件的方法。提供了具有器件隔离区域和形成在其上的栅极氧化物层的半导体衬底。形成第一导电层以覆盖器件隔离区域和栅极氧化物层。如果形成在器件隔离区上以覆盖第一导电层的一部分的介电层。在介电层和第一导电层上形成第二导电层。将第二导电层和第一导电层图案化以形成电容器和栅极。

36. 发明授权

US5950097A Advanced isolation scheme for deep submicron technology 失效
标题翻译：深亚微米技术的先进隔离方案
公开(公告)号：US5950097A
公开(公告)日：1999-09-07
申请号：US698828
申请日：1996-08-16
申请人： Kuang-Yeh Chang , Yowjuang William Liu , Mark I. Gardner , Frederick N. Hause
发明人： Kuang-Yeh Chang , Yowjuang William Liu , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/20 , H01L21/762 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76294
摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.
摘要翻译：氧化物层在半导体本体上热生长，并且在氧化物层中蚀刻开口以暴露半导体本体的表面的部分。然后，外延区域从半导体本体生长到氧化物层中的开口中，这些外延区域最终将成为器件的有源区域。

37. 发明授权

US5930628A Method for fabricating one time programmable read only memory 失效
标题翻译：制造一次性可编程只读存储器的方法
公开(公告)号：US5930628A
公开(公告)日：1999-07-27
申请号：US093691
申请日：1998-06-09
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： H01L21/8247 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/11543 , H01L27/11546
摘要： A method for fabricating a one-time programmable read only memory includes forming a spacer to cover the sides of the periphery transistor gate before patterning the control gate, then patterning the polysilicon layer to form a floating gate, and then forming a heavily concentrated ion implantation area in the substrate beneath the sides of the floating gate. Since the spacer is deposited on the sidewalls of the polysilicon layer within the peripheral area, but not the memory cell area, the efficiency of programming is improved. In addition, there is no need for extra ion implantation processes for make up for the lower programming efficiency caused by the spacers. Furthermore, the leakage current that is caused by the damage to the field oxide generated during the etching back process for forming the spacer is eliminated.
摘要翻译：一种制造一次性可编程只读存储器的方法包括在图案化控制栅极之前形成间隔物以覆盖外围晶体管栅极的侧面，然后构图多晶硅层以形成浮置栅极，然后形成大量浓缩的离子注入位于浮动门侧面底部的区域。由于间隔物沉积在外围区域内的多晶硅层的侧壁上，而不是存储单元区域，因此编程效率得到改善。此外，不需要额外的离子注入工艺来弥补由间隔物引起的较低编程效率。此外，消除了在用于形成间隔物的蚀刻回加工过程中产生的对场氧化物的损伤引起的漏电流。

38. 发明授权

US5920499A Method of decoding a diode type read only memory 失效
标题翻译：二极管型只读存储器的解码方法
公开(公告)号：US5920499A
公开(公告)日：1999-07-06
申请号：US969151
申请日：1997-11-12
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： G11C17/06
CPC分类号： G11C17/06
摘要： A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative high voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.
摘要翻译：二极管型只读存储器（ROM）包括二极管作为存储单元。二极管是逻辑电平“on”存储器单元，并且耦合到ROM中的一个字线和一个位线。给予耦合到二极管的位线的相对高电压，并且相应的高电压被给予相应的字线。因此，可以读出保存在二极管中的数据。

39. 发明授权

US5891777A Method of making a ROM diode 失效
标题翻译：制造ROM二极管的方法
公开(公告)号：US5891777A
公开(公告)日：1999-04-06
申请号：US808258
申请日：1997-02-28
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： H01L21/8229 , H01L27/102 , H01L21/8246
CPC分类号： H01L21/8229 , H01L27/1021 , Y10S257/91
摘要： A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The P-type substrate is doped using first N-type ions to form a plurality of essentially parallel N-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the N-pole regions. The P-type substrate is doped and annealed, to form a plurality of N-type diffusion regions under the exposed portions of the N-pole regions. The N-pole regions are doped and annealed, to form a plurality of P-type diffusion regions in the exposed portions of the N-pole regions. A metal layer is formed which fills the contact windows. The metal layer is patterned to form a plurality of essentially parallel word lines. A read only memory device is proposed that includes a plurality of essentially parallel N-pole regions are located on a substrate. A plurality of N-type diffusion regions are located under selected portions of respective N-pole regions. A plurality of P-type diffusion regions are located over respective selected portions of the N-pole regions. Each respective P-type diffusion region and associated N-pole region forms a diode.
摘要翻译：形成ROM的方法包括在P型衬底上形成衬垫氧化层，在衬垫氧化层上形成氮化硅层并对氮化硅层进行构图。在衬底上形成场氧化物层。去除氮化硅层。使用第一N型离子掺杂P型衬底，以形成多个基本上平行的N极区域。在场氧化物层上形成绝缘层。在绝缘层内形成多个接触窗以暴露N极区域的一部分。 P型衬底被掺杂和退火，以在N极区域的暴露部分之下形成多个N型扩散区域。 N极区域被掺杂并退火，以在N极区域的露出部分中形成多个P型扩散区域。形成填充接触窗的金属层。将金属层图案化以形成多个基本平行的字线。提出了一种只读存储器件，其包括位于衬底上的多个基本平行的N极区域。多个N型扩散区域位于各个N极区域的选定部分的下方。多个P型扩散区域位于N极区域的各个选定部分上。每个相应的P型扩散区和相关的N极区形成二极管。

40. 发明授权

US5811347A Nitrogenated trench liner for improved shallow trench isolation 失效
标题翻译：氮化沟槽衬垫，用于改善浅沟槽隔离
公开(公告)号：US5811347A
公开(公告)日：1998-09-22
申请号：US641028
申请日：1996-04-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/314 , H01L21/318 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3144 , H01L21/3185 , H01L21/76224 , Y10S148/05
摘要： A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO.sub.2 trench liner and subsequently implanting the SiO.sub.2 trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.
摘要翻译：一种在半导体衬底内的有源区之间形成改进的隔离沟槽的方法。改进的方法包括氮含量为约0.5至2.0％的沟槽衬垫。在硅衬底上形成衬垫层，并在衬垫层上形成氮化物层。此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。然后形成沟槽衬垫，并且氮结合到沟槽衬里中。通过在存在氮气环境的情况下形成沟槽衬垫或通过形成纯的SiO 2沟槽衬垫并随后用氮气注入SiO 2沟槽衬垫，可以将氮掺入到沟槽衬里中。在形成氮化沟槽衬垫之后，用优选由CVD氧化物构成的电介质填充沟槽。此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

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