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31. 发明授权

US06337822B1 Write masking in a semiconductor memory device 有权
标题翻译：在半导体存储器件中写掩蔽
公开(公告)号：US06337822B1
公开(公告)日：2002-01-08
申请号：US09604585
申请日：2000-06-27
申请人： Jin-seok Kwak , Yong-ho Shim
发明人： Jin-seok Kwak , Yong-ho Shim
IPC分类号： G11C700
CPC分类号： G11C7/1006
摘要： A semiconductor memory device having a write masking function and a write masking method are provided. The semiconductor memory device includes a plurality of write bit lines, a plurality of write word lines, a plurality of write drivers, a plurality of MOS transistors, a plurality of latch circuits, and a plurality of precharge controllers. Each of the write drivers receives input data, a write enable signal and a write masking signal, outputs the input data when the write enable signal is activated and the write masking signal is deactivated, and does not output the input data when the write masking signal is activated. Each of the latch circuits includes an inverter having a large driving capacity and an inverter having a small driving capacity. When a precharge signal is activated, each of the precharge controllers precharges a corresponding write bit line to the logic threshold voltage of the inverter having the large driving capacity. Accordingly, memory cells are reliably masked in a write masking mode.
摘要翻译：提供一种具有写入屏蔽功能和写入掩蔽方法的半导体存储器件。半导体存储器件包括多个写入位线，多个写入字线，多个写入驱动器，多个MOS晶体管，多个锁存电路和多个预充电控制器。每个写入驱动器接收输入数据，写使能信号和写掩蔽信号，当写使能信号被激活并且写屏蔽信号被去激活时输出输入数据，并且当写屏蔽信号被激活。每个锁存电路包括具有大驱动能力的逆变器和具有小驱动能力的逆变器。当预充电信号被激活时，每个预充电控制器将相应的写位线预充电到具有大驱动能力的逆变器的逻辑阈值电压。因此，以写入掩蔽模式可靠地掩蔽存储器单元。

32. 发明授权

US06320801B1 Redundancy circuit and redundancy method for semiconductor memory device 有权
标题翻译：半导体存储器件的冗余电路和冗余方法
公开(公告)号：US06320801B1
公开(公告)日：2001-11-20
申请号：US09643323
申请日：2000-08-21
申请人： Jin Seok Kwak
发明人： Jin Seok Kwak
IPC分类号： G11C2900
CPC分类号： G11C29/808 , G11C29/846
摘要： A redundancy circuit of a semiconductor memory device includes a mode setting circuit that generates mode signal, an input selecting circuit that generates selecting signal in response to the mode signals, and a decoding circuit that, in response to the mode selecting signals, generates decoding signals. The redundancy mode signals include a bank redundancy mode signal, an array redundancy mode signal, and a column address group redundancy mode signal. The selecting signal identifies a bank in bank redundancy mode, an array in an array redundancy mode, and a column address group in column address group redundancy mode. The decoding signals initiate a replacement of a data I/O line pair associated to a defective memory cell in the semiconductor memory device. A redundancy method includes: generating the redundancy mode signals; generating the selecting signal in response to the redundancy mode signals; and generating the decoding signals.
摘要翻译：半导体存储器件的冗余电路包括产生模式信号的模式设置电路，响应于模式信号产生选择信号的输入选择电路，以及响应于模式选择信号产生解码信号的解码电路。冗余模式信号包括存储体冗余模式信号，阵列冗余模式信号和列地址组冗余模式信号。选择信号以行冗余模式识别存储体，阵列冗余模式中的阵列，列地址组冗余模式中的列地址组。解码信号开始替换与半导体存储器件中的有缺陷的存储器单元相关联的数据I / O线对。冗余方法包括：产生冗余模式信号; 响应冗余模式信号产生选择信号; 并产生解码信号。

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