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31. 发明授权

US6164295A CVD apparatus with high throughput and cleaning method therefor 失效
标题翻译：高产量的CVD装置及其清洗方法
公开(公告)号：US6164295A
公开(公告)日：2000-12-26
申请号：US848264
申请日：1997-04-29
申请人： Akio Ui , Naruhiko Kaji , Hideshi Miyajima , Nobuo Hayasaka
发明人： Akio Ui , Naruhiko Kaji , Hideshi Miyajima , Nobuo Hayasaka
IPC分类号： B08B7/00 , C23C16/44 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3065 , H01L21/31
CPC分类号： C23C16/4405 , B08B7/0035 , H01L21/02049
摘要： There is provided a CVD apparatus and a cleaning method which can precisely perform cleaning at a high speed, in order to increase the throughput of a CVD apparatus. A film formation gas (e.g., SiH.sub.4 and O.sub.2 gases) is introduced from a source gas supply pipe into a chamber to form a silicon oxide film (SiO.sub.2) on a wafer placed on a susceptor by using a plasma or the like. A thin film (SiO.sub.2) mainly consisting of silicon and oxygen, an imperfect oxide film of silicon, or the like also attaches to a wall surface and the respective surfaces of a window plate, a vacuum seal portion, the susceptor, an electrode, an insulator, an exhaust pipe, and the like in the chamber. An HF-based gas supply system for a cleaning etching gas is arranged to clean the interior of the chamber of the CVD apparatus. Particularly, a film formed with a source gas of Si.sub.x H.sub.2x+2 (x=1, 2, 3) and O.sub.2 is more perfect than an imperfect oxide film (e.g., TEOS) formed with an organic silicon source gas, so that bonding is strong, and the etching rate decreases in plasma cleaning and the like. Cleaning with the HF gas according to this invention is very effective.
摘要翻译：提供了能够高精度地进行清洗的CVD装置和清洗方法，以提高CVD装置的生产量。将成膜气体（例如SiH 4和O 2气体）从源气体供给管引入室中，通过使用等离子体等在放置在基座上的晶片上形成氧化硅膜（SiO 2）。主要由硅和氧组成的薄膜（SiO 2），硅的不完全氧化膜等也附着在壁面，窗板，真空密封部分，基座，电极，绝缘体，排气管等。布置用于清洁蚀刻气体的基于HF的气体供应系统以清洁CVD设备的室的内部。特别地，形成有SixH2x + 2（x = 1,2,3）和O2的源气体的膜比用有机硅源气体形成的不完全氧化膜（例如TEOS）更完美，使得结合强，并且等离子体清洗等中的蚀刻速率降低。使用根据本发明的HF气体的清洁是非常有效的。

32. 发明授权

US5561082A Method for forming an electrode and/or wiring layer by reducing copper oxide or silver oxide 失效
标题翻译：通过还原氧化铜或氧化银形成电极和/或布线层的方法
公开(公告)号：US5561082A
公开(公告)日：1996-10-01
申请号：US405948
申请日：1995-03-17
申请人： Mie Matsuo , Haruo Okano , Nobuo Hayasaka , Kyoichi Suguro , Hideshi Miyajima , Jun-ichi Wada
发明人： Mie Matsuo , Haruo Okano , Nobuo Hayasaka , Kyoichi Suguro , Hideshi Miyajima , Jun-ichi Wada
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , H01L21/28
CPC分类号： H01L21/76877 , H01L21/28518 , H01L21/76823 , H01L21/76838 , H01L21/76849 , H01L23/5283 , H01L23/53238 , H01L2924/0002
摘要： The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.
摘要翻译：本发明提供了一种制造半导体器件的方法，包括以下步骤：形成由金属氧化物制成的金属氧化物膜，其标准自由能的降低小于氧化物或氧化碳的标准自由能的降低，对形成在半导体基板上的绝缘膜，通过对金属氧化物膜进行处理形成金属氧化物膜图案，并将所述金属氧化物图案转换成电极和由作为主要成分的金属制成的布线中的至少一个通过在80℃〜500℃的温度下还原金属氧化物膜图案来构成金属氧化物。

33. 发明申请

US20140027914A1 PROTECTION OF UNDER-LAYER CONDUCTIVE PATHWAY 审中-公开
标题翻译：保护层间导电路径
公开(公告)号：US20140027914A1
公开(公告)日：2014-01-30
申请号：US13556338
申请日：2012-07-24
申请人： Hideyuki Tomizawa , Masao Ishikawa , Hideshi Miyajima
发明人： Hideyuki Tomizawa , Masao Ishikawa , Hideshi Miyajima
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L21/76867 , H01L21/76804 , H01L21/76805 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76849 , H01L21/76856 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods are presented for preventing removal of material comprising a metal gate during removal of a mask layer in a semiconductor structure. Upon exposure of the metal line during formation of a via opening the exposed portion of the metal line undergoes chemical modification to form a passivation layer. The passivation layer is subsequently covered by an etch selectivity layer, wherein the etch selectivity layer prevents removal of at least one of a portion of the metal line or the passivation layer during removal of a hard mask layer comprising the semiconductor structure. In an alternate approach, the metal line is formed with a capping layer which, following exposure by a via opening formed in the semiconductor structure, is chemically modified to form a layer having etch selectivity to acts as a protective layer during removal of a hard mask layer comprising the semiconductor layer.
摘要翻译：提出了用于在半导体结构中去除掩模层期间防止包括金属栅极的材料的去除的系统和方法。在形成通路孔期间暴露金属线时，金属线的暴露部分经历化学改性以形成钝化层。钝化层随后被蚀刻选择性层覆盖，其中，在去除包含半导体结构的硬掩模层期间，蚀刻选择层防止去除金属线或钝化层的一部分中的至少一个。在替代方法中，金属线形成有覆盖层，其在通过形成在半导体结构中的通孔开口暴露之后被化学修饰以形成具有蚀刻选择性的层，以在去除硬掩模期间用作保护层层包括半导体层。

34. 发明申请

US20070093052A1 SEMICONDUCTOR DEVICE HAVE MULTIPLE WIRING LAYERS AND METHOD OF PRODUCING THE SAME 失效
标题翻译：半导体器件具有多个布线层及其制造方法
公开(公告)号：US20070093052A1
公开(公告)日：2007-04-26
申请号：US11565530
申请日：2006-11-30
申请人： Yoshiaki Shimooka , Hideki Shibata , Hideshi Miyajima , Kazuhiro Tomioka
发明人： Yoshiaki Shimooka , Hideki Shibata , Hideshi Miyajima , Kazuhiro Tomioka
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76807 , H01L21/7682 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
摘要翻译：一种制造具有多个布线层的半导体器件的方法形成第一层间绝缘膜，在第一层间绝缘膜中形成用于布线的多个沟槽，在沟槽中填充金属膜以形成布线，蚀刻第一夹层将布线作为掩模，并且去除布线之间的层间绝缘膜以提供要填充的沟槽，并且在要填充的沟槽中填充由低介电常数材料制成的第二层间绝缘膜。

35. 发明申请

US20060199373A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060199373A1
公开(公告)日：2006-09-07
申请号：US11360703
申请日：2006-02-24
申请人： Hideshi Miyajima , Hideaki Masuda , Tsutomu Shimayama , Shunichi Shibuki
发明人： Hideshi Miyajima , Hideaki Masuda , Tsutomu Shimayama , Shunichi Shibuki
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/0234 , H01L21/02351 , H01L21/31633 , H01L21/3185 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76835
摘要： A manufacturing method of a semiconductor device, comprising providing a low-relative-dielectric-constant film above a substrate containing at least oxygen and having a relative dielectric constant of 3.3 or more, a conductor being to be buried in the film, performing a plasma processing by discharging a gas containing a noble gas as a main component to the film, the plasma processing being executed while the substrate above which the film is provided is storing in a processing chamber having an inside covered with a material composed of an element except for oxygen and substantially set under an oxygen-free atmosphere, and providing a first insulating film above the low-relative-dielectric-constant film by a plasma CVD method, being made of a material containing at least one of a material containing oxygen and a material containing an element reacting with oxygen, a conductor being to be buried in the first insulating film.
摘要翻译：一种半导体器件的制造方法，包括在至少包含氧并且相对介电常数为3.3以上的衬底上提供低相对介电常数膜，导体将被埋在膜中，执行等离子体通过将含有惰性气体作为主要成分的气体排放到膜上进行处理，在其上设置有膜的基板上存储等离子体处理的处理室中，该处理室具有由除了氧并基本上设置在无氧气氛下，并且通过等离子体CVD法在低相对介电常数膜之上提供第一绝缘膜，该材料由含有氧和材料的材料中的至少一种含有与氧反应的元素，导体将被埋在第一绝缘膜中。

36. 发明申请

US20050112863A1 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050112863A1
公开(公告)日：2005-05-26
申请号：US10974850
申请日：2004-10-28
申请人： Hideshi Miyajima
发明人： Hideshi Miyajima
IPC分类号： H01L21/00 , H01L21/316 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76828 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： According to an aspect of the invention, there is provided a method for fabricating a semiconductor device, comprising forming at least one interconnection layer having a low dielectric constant insulating film and an interconnection buried in the low dielectric constant insulating film, forming a trench or a hole extending in the interconnection layer, performing heat treatment for the interconnection layer having the trench or the hole, and burying a material in the trench or the hole.
摘要翻译：根据本发明的一个方面，提供了一种制造半导体器件的方法，包括形成具有低介电常数绝缘膜和埋在低介电常数绝缘膜中的互连的至少一个互连层，形成沟槽或在互连层中延伸的孔，对具有沟槽或孔的互连层进行热处理，并将材料埋入沟槽或孔中。

37. 发明授权

US06746969B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06746969B2
公开(公告)日：2004-06-08
申请号：US09982003
申请日：2001-10-19
申请人： Miyoko Shimada , Hideshi Miyajima , Rempei Nakata , Hideto Matsuyama , Katsuya Okumura , Masahiko Hasunuma , Nobuo Hayasaka
发明人： Miyoko Shimada , Hideshi Miyajima , Rempei Nakata , Hideto Matsuyama , Katsuya Okumura , Masahiko Hasunuma , Nobuo Hayasaka
IPC分类号： H01L2131
CPC分类号： H01L21/02351 , H01L21/02126 , H01L21/02137 , H01L21/02312 , H01L21/02337 , H01L21/2636 , H01L21/3122 , H01L21/316 , H01L21/76825 , H01L21/76828 , H01L21/76834
摘要： A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.
摘要翻译：一种制造半导体器件的方法包括：准备待处理的衬底，以及在衬底上方形成绝缘膜，该绝缘膜包括在衬底上施加绝缘膜原料，所述绝缘膜原料包括物质或物质的前体所述绝缘膜包含该物质，通过在反应器室中加热基板同时在基板上照射电子束来固化绝缘膜原料，改变选自反应器室中的压力，温度的基板，当电子束被照射在基板上时，具有暴露于其中的基板的气体类型，引入反应室的气体流量，基板的位置和每单位时间入射到基板的电子量。

38. 发明授权

US06737363B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06737363B2
公开(公告)日：2004-05-18
申请号：US09961490
申请日：2001-09-25
申请人： Hideshi Miyajima , Nobuhide Yamada , Nobuo Hayasaka , Nobuyuki Kurashima
发明人： Hideshi Miyajima , Nobuhide Yamada , Nobuo Hayasaka , Nobuyuki Kurashima
IPC分类号： H01L2144
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02343 , H01L21/02359 , H01L21/31053 , H01L21/31058 , H01L21/3122 , H01L21/76819
摘要： A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a low dielectric constant insulating film having a siloxane bond as main skeleton on a semiconductor substrate, causing a surfactant to permeate the low dielectric constant insulating film, and conducting a predetermined step on the low dielectric constant insulating film permeated with the surfactant in a state adapted to be exposed to water.
摘要翻译：根据本发明的一个方面的制造半导体器件的方法包括在半导体衬底上形成具有硅氧烷键作为主骨架的低介电常数绝缘膜，使表面活性剂渗入低介电常数绝缘膜，并进行在适于暴露于水的状态下用表面活性剂渗透的低介电常数绝缘膜上的预定步骤。

39. 发明授权

US06703302B2 Method of making a low dielectric insulation layer 失效
标题翻译：制造低介电绝缘层的方法
公开(公告)号：US06703302B2
公开(公告)日：2004-03-09
申请号：US10141578
申请日：2002-05-09
申请人： Hideshi Miyajima , Miyoko Shimada , Rempei Nakata
发明人： Hideshi Miyajima , Miyoko Shimada , Rempei Nakata
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/76828
摘要： A method for manufacturing a semiconductor device, comprising forming a low dielectric constant insulating film containing Si atoms over a semiconductor substrate, heating the low dielectric constant insulating film while irradiating the low dielectric constant insulating film with an electron beam, and exposing the low dielectric constant insulating film during or after the heating to a gas promoting the bond formation of the Si atoms.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成含有Si原子的低介电常数绝缘膜，在用电子束照射低介电常数绝缘膜的同时加热低介电常数绝缘膜，并暴露低介电常数绝缘膜在加热期间或之后至促进Si原子的键形成的气体。

40. 发明授权

US06614096B2 Method for manufacturing a semiconductor device and a semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US06614096B2
公开(公告)日：2003-09-02
申请号：US10126591
申请日：2002-04-22
申请人： Akihiro Kojima , Hideshi Miyajima
发明人： Akihiro Kojima , Hideshi Miyajima
IPC分类号： H01L2358
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02282 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/314 , H01L21/3144 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76822 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a semiconductor device, which comprises the steps of forming a first insulating film made of a low dielectric constant material and containing carbon, subjecting the first insulating film to a surface treatment to reduce the carbon concentration of surface layer of the first insulating film, thus turning the surface layer into a low carbon concentration layer, forming a second insulating film on the low carbon concentration layer, forming a groove in the first and second insulating films for burying a metal therein, burying the metal in the groove formed in the first and second insulating films, and polishing a surface of the metal buried in the groove to thereby form a metal wiring.
摘要翻译：公开了一种半导体器件的制造方法，其包括以下步骤：形成由低介电常数材料制成并含有碳的第一绝缘膜，对第一绝缘膜进行表面处理以降低表面层的碳浓度第一绝缘膜，从而将表面层转化为低碳浓度层，在低碳浓度层上形成第二绝缘膜，在第一和第二绝缘膜中形成用于将金属埋入其中的沟槽，将金属埋入沟槽形成在第一绝缘膜和第二绝缘膜中，并且抛光埋在槽中的金属的表面，从而形成金属布线。

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