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31. 发明授权

US07410892B2 Methods of fabricating integrated circuit devices having self-aligned contact structures 有权
标题翻译：制造具有自对准接触结构的集成电路器件的方法
公开(公告)号：US07410892B2
公开(公告)日：2008-08-12
申请号：US11375914
申请日：2006-03-15
申请人： Hee-Sook Park , Gil-Heyun Choi , Sang-Bom Kang , Kwang-Jin Moon , Hyun-Su Kim , Seung-Gil Yang
发明人： Hee-Sook Park , Gil-Heyun Choi , Sang-Bom Kang , Kwang-Jin Moon , Hyun-Su Kim , Seung-Gil Yang
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L27/10885 , H01L21/76831 , H01L21/76897 , H01L24/02 , H01L27/10855 , H01L27/10888 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/00
摘要： An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.
摘要翻译：集成电路器件，例如存储器件，包括衬底，衬底上的第一绝缘层，以及设置在与衬底直接接触的第一绝缘层中的接触焊盘。第二绝缘层设置在第一绝缘层上。导电图案，例如镶嵌位线，设置在第二绝缘层中。导电插塞延伸穿过第二绝缘层以接触接触焊盘并且与导电图案自对准。绝缘膜可以分离导电图案和导电插头。胶层可以设置在导电图案和第二绝缘层之间。该器件还可以包括在第二绝缘层和导电图案上的第三绝缘层，并且导电插塞可延伸穿过第二和第三绝缘层。

32. 发明申请

US20080079056A1 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080079056A1
公开(公告)日：2008-04-03
申请号：US11648595
申请日：2007-01-03
申请人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
发明人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
IPC分类号： H01L29/76
CPC分类号： H01L29/4941 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/11568 , H01L29/513
摘要： A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.
摘要翻译：半导体存储器件，例如电荷俘获型非易失性存储器件，可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。电荷捕获结构可以包括隧道氧化物层图案，电荷俘获层图案和含铝三级金属氧化物的介电层图案。栅极结构可以包括栅极氧化物层图案，多晶硅层图案和含铝三次金属硅化物的欧姆层图案。第一电极和第二电极可以形成在电荷捕获结构上。可以在栅极结构上设置下电极和上电极。电介质层图案可以具有更高的介电常数，并且欧姆层图案可以具有改善的热稳定性，从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

33. 发明申请

US20080014700A1 Methods for fabricating improved gate dielectrics 失效
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US20080014700A1
公开(公告)日：2008-01-17
申请号：US11806338
申请日：2007-05-31
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

34. 发明授权

US07223689B2 Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer 有权
标题翻译：在形成阻挡金属层的同时形成欧姆层的半导体器件中形成金属接触的方法
公开(公告)号：US07223689B2
公开(公告)日：2007-05-29
申请号：US11112356
申请日：2005-04-22
申请人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
发明人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/76846 , H01L21/76855 , H01L21/76858
摘要： A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
摘要翻译：通过在硅衬底上形成具有接触孔的绝缘层，形成半导体器件中的金属接触。钴层形成在接触孔的底壁和内壁上。在钴层上形成钛层的同时，在接触孔的底部形成钴硅化物层。在钛层上形成插塞以填充接触孔。

35. 发明申请

US20070052043A1 Multilayer gate electrode, semiconductor device having the same and method of fabricating the same 审中-公开
标题翻译：多层栅电极，与其相同的半导体器件及其制造方法
公开(公告)号：US20070052043A1
公开(公告)日：2007-03-08
申请号：US11516633
申请日：2006-09-07
申请人： Tae-Ho Cha , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Byung-Hee Kim
发明人： Tae-Ho Cha , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Byung-Hee Kim
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/823828
摘要： Example embodiments relate to a multilayer gate electrode, a semiconductor device having the same and methods of fabricating the same. Other example embodiments relate to a semiconductor device with a multilayer gate electrode which is relatively stable at higher temperatures, has improved resistance characteristics and improved reliability, and methods of fabricating the same. The multilayer gate electrode may include a polycrystalline semiconductor layer on the gate insulating layer and doped with conductive type impurities, an ohmic contact layer on the polycrystalline semiconductor layer and including tungsten (W1−x) and non-tungsten metal (Mx, x=about 0.01 to about 0.55), a metal barrier layer on the ohmic contact layer and a refractory metal layer on the metal barrier layer. The semiconductor device including a conductive type transistor may include a semiconductor substrate, a conductive type source/drain region in the semiconductor substrate, a gate insulating layer on a channel region between the source/drain regions and the multilayer gate electrode.
摘要翻译：示例性实施例涉及多层栅电极，具有该多层栅电极的半导体器件及其制造方法。其他示例性实施例涉及具有多层栅电极的半导体器件，其在较高温度下相对稳定，具有改善的电阻特性和改善的可靠性，及其制造方法。多层栅电极可以包括在栅极绝缘层上并掺杂有导电类型杂质的多晶半导体层，多晶半导体层上的欧姆接触层，并且包括钨（W 1-x N）钨金属（M x x x，x =约0.01至约0.55），欧姆接触层上的金属阻挡层和金属阻挡层上的难熔金属层。包括导电型晶体管的半导体器件可以包括半导体衬底，半导体衬底中的导电型源极/漏极区域，在源极/漏极区域和多层栅极电极之间的沟道区域上的栅极绝缘层。

36. 发明申请

US20060115967A1 Methods of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060115967A1
公开(公告)日：2006-06-01
申请号：US11246791
申请日：2005-10-07
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Sun-Pil Youn , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Sun-Pil Youn , Woong-Hee Sohn
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/823828
摘要： In a method of manufacturing a semiconductor device including a polysilicon layer on which a heat treatment is performed in hydrogen atmosphere, a preliminary polysilicon layer is formed on a semiconductor substrate. Fluorine (F) impurities are implanted onto the preliminary polysilicon layer, so that the preliminary polysilicon layer is formed into a polysilicon layer. A main heat treatment is performed on the polysilicon layer, thereby preventing a void caused by the fluorine (F) in the polysilicon layer. A subsidiary heat treatment is further performed on the polysilicon layer prior to the main heat treatment, thereby activating dopants in the polysilicon layer. Electrical characteristics and performance of a semiconductor device are improved since the void is sufficiently prevented in the polysilicon layer.
摘要翻译：在制造包括在氢气氛中进行热处理的多晶硅层的半导体器件的方法中，在半导体衬底上形成初步多晶硅层。将氟（F）杂质注入到初步多晶硅层上，使得初步多晶硅层形成为多晶硅层。在多晶硅层上进行主要的热处理，从而防止由多晶硅层中的氟（F）引起的空隙。在主要热处理之前在多晶硅层上进一步进行辅助热处理，由此激活多晶硅层中的掺杂剂。改善了半导体器件的电特性和性能，因为在多晶硅层中充分防止了空隙。

37. 发明授权

US07045842B2 Integrated circuit devices having self-aligned contact structures 有权
标题翻译：具有自对准接触结构的集成电路器件
公开(公告)号：US07045842B2
公开(公告)日：2006-05-16
申请号：US10779440
申请日：2004-02-13
申请人： Hee-Sook Park , Gil-Heyun Choi , Sang-Bom Kang , Kwang-Jin Moon , Hyun-Su Kim , Seung-Gil Yang
发明人： Hee-Sook Park , Gil-Heyun Choi , Sang-Bom Kang , Kwang-Jin Moon , Hyun-Su Kim , Seung-Gil Yang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10885 , H01L21/76831 , H01L21/76897 , H01L24/02 , H01L27/10855 , H01L27/10888 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/00
摘要： An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.
摘要翻译：集成电路器件，例如存储器件，包括衬底，衬底上的第一绝缘层，以及设置在与衬底直接接触的第一绝缘层中的接触焊盘。第二绝缘层设置在第一绝缘层上。导电图案，例如镶嵌位线，设置在第二绝缘层中。导电插塞延伸穿过第二绝缘层以接触接触焊盘并且与导电图案自对准。绝缘膜可以分离导电图案和导电插头。胶层可以设置在导电图案和第二绝缘层之间。该器件还可以包括在第二绝缘层和导电图案上的第三绝缘层，并且导电插塞可延伸穿过第二和第三绝缘层。

38. 发明申请

US20060079075A1 Gate structures with silicide sidewall barriers and methods of manufacturing the same 审中-公开
标题翻译：具有硅化物侧壁障碍的门结构及其制造方法
公开(公告)号：US20060079075A1
公开(公告)日：2006-04-13
申请号：US11201736
申请日：2005-08-11
申请人： Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jong-Ryeol Yoo , Woong-Hee Sohn
发明人： Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jong-Ryeol Yoo , Woong-Hee Sohn
IPC分类号： H01L21/3205
CPC分类号： H01L21/28061 , H01L29/4958 , H01L29/517
摘要： A gate structure includes a gate insulation layer on a substrate, a polysilicon layer pattern on the gate insulation layer, a composite metal layer pattern on the polysilicon layer pattern, and a metal silicide layer pattern on a sidewall of the composite metal layer pattern.
摘要翻译：栅极结构包括在衬底上的栅极绝缘层，栅极绝缘层上的多晶硅层图案，多晶硅层图案上的复合金属层图案以及复合金属层图案的侧壁上的金属硅化物层图案。

39. 发明申请

US20050266665A1 Methods of manufacturing semiconductor devices with gate structures having an oxide layer on the sidewalls thereof and related processing apparatus 审中-公开
标题翻译：制造具有在其侧壁上具有氧化物层的栅极结构的半导体器件的方法和相关的处理装置
公开(公告)号：US20050266665A1
公开(公告)日：2005-12-01
申请号：US11141401
申请日：2005-05-31
申请人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Shon , Jong-Ryeol Yoo
发明人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Shon , Jong-Ryeol Yoo
IPC分类号： H01L21/336 , H01L21/28 , H01L21/3205 , H01L21/321
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/32105
摘要： In a method of manufacturing a semiconductor device, a gate structure having a conductive layer pattern is formed on a substrate. The gate structure is then annealed. Oxygen radicals are applied to the gate structure to form an oxide layer on a sidewall of the conductive layer pattern.
摘要翻译：在制造半导体器件的方法中，在衬底上形成具有导电层图案的栅极结构。然后将栅极结构退火。将氧自由基施加到栅极结构以在导电层图案的侧壁上形成氧化物层。

40. 发明申请

US20050054183A1 Method for forming contact having low resistivity using porous plug and method for forming semiconductor devices using the same 失效
标题翻译：使用多孔塞形成具有低电阻率的接触的方法和使用其形成半导体器件的方法
公开(公告)号：US20050054183A1
公开(公告)日：2005-03-10
申请号：US10895190
申请日：2004-07-19
申请人： Hee-Sook Park
发明人： Hee-Sook Park
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L27/105 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/10855 , H01L21/76802 , H01L21/76808 , H01L27/105 , H01L27/10894
摘要： A method for forming a contact of a semiconductor device is disclosed. A first interlevel dielectric (ILD) layer is formed on a conductive region, e.g., an active region. The first ILD layer is etched to form a first contact hole therein to expose the conductive region. The first contact hole is filled with a porous layer having a high etch selectivity with respect to the first ILD layer to form a porous plug therein. Next, a second ILD layer is formed overlying the porous plug. The second ILD layer is etched to form a second contact hole therein to expose the porous plug. The porous plug in the first contact hole is removed. The first and second contact holes are filled with a conductive material to form a contact plug. During this contact formation process, the active region or the conductive region of the semiconductor substrate can be protected with the porous plug. Thus, the electrical characteristics degradation caused by dopant diffusion resulting from a thermal process during contact formation can be avoided.
摘要翻译：公开了一种用于形成半导体器件的接触的方法。在导电区域（例如有源区）上形成第一层间电介质（ILD）层。蚀刻第一ILD层以在其中形成第一接触孔以暴露导电区域。第一接触孔填充有相对于第一ILD层具有高蚀刻选择性的多孔层，以在其中形成多孔塞。接下来，形成覆盖多孔塞的第二ILD层。蚀刻第二ILD层以在其中形成第二接触孔以暴露多孔塞。去除第一接触孔中的多孔塞。第一和第二接触孔填充有导电材料以形成接触塞。在该接触形成过程中，半导体衬底的有源区或导电区可以用多孔插塞保护。因此，可以避免在接触形成期间由热处理引起的掺杂剂扩散引起的电特性劣化。

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