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31. 发明授权

US08803567B2 Frequency multiplier system and method of multiplying frequency 有权
标题翻译：倍频系统和倍频方法
公开(公告)号：US08803567B2
公开(公告)日：2014-08-12
申请号：US13208346
申请日：2011-08-12
申请人： Yong Quan , Guosheng Wu
发明人： Yong Quan , Guosheng Wu
IPC分类号： H03B19/00
CPC分类号： G06F1/08
摘要： A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N≧2, includes a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency. And a method of multiplying frequency is provided. The present invention does not need feedback circuits, and therefore is stable and fast-speed, saves area, and reduces energy consumption.
摘要翻译：一种倍频器系统，用于在处理输入时钟之后输出N倍频的单相时钟，N≥2，包括接收输入时钟的分频器，与分频器连接的内插器，与内插器连接的相位均衡器，以及与所述相位均衡器连接的组合逻辑电路，其中所述分频器将具有作为输入时钟的一半的两相频率的正交时钟输出到所述内插器，所述内插器将2N相时钟输出到所述相位均衡器，相位均衡器均匀化2N相时钟的相位偏移，组合逻辑电路将均匀化的2N相时钟合成为N倍频的单相时钟。并提供一种倍频方法。本发明不需要反馈电路，因此是稳定和快速的，节省了面积，并且降低了能量消耗。

32. 发明授权

US08476950B2 High-speed latch circuit 失效
标题翻译：高速锁存电路
公开(公告)号：US08476950B2
公开(公告)日：2013-07-02
申请号：US13224098
申请日：2011-09-01
申请人： Yong Quan , Guosheng Wu
发明人： Yong Quan , Guosheng Wu
IPC分类号： H03K3/356
CPC分类号： H03K3/356139
摘要： A high-speed latch circuit includes a latching unit for latching an inputted signal, a signal input unit connected to the latching unit and a clock control unit connected to the signal input unit. The clock control unit includes a first switch element, a second switch element connected to the first switch element and an inverter connected to the second switch element. The first switch element and the inverter are both connected to a clock signal input end. The high-speed latch circuit of the present invention has a simple circuit structure, shortens the triggering time of the signal and reduces chances of wrong triggering.
摘要翻译：高速锁存电路包括用于锁存输入信号的锁存单元，连接到锁存单元的信号输入单元和连接到信号输入单元的时钟控制单元。时钟控制单元包括第一开关元件，连接到第一开关元件的第二开关元件和连接到第二开关元件的反相器。第一开关元件和反相器都连接到时钟信号输入端。本发明的高速锁存电路具有简单的电路结构，缩短了信号的触发时间，减少了触发错误的可能性。

33. 发明申请

US20120134458A1 Frequency detector and method for detecting frequencies 有权
标题翻译：频率检测器和频率检测方法
公开(公告)号：US20120134458A1
公开(公告)日：2012-05-31
申请号：US13215101
申请日：2011-08-22
申请人： Yong Quan , Guosheng Wu
发明人： Yong Quan , Guosheng Wu
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： A frequency detector includes a multi-phase clock generation unit, a sampling unit connected to the multi-phase clock generation unit and a digital logic unit connected to the sampling unit. An inputted single-phase clock is received by the multi-phase clock generation unit and transformed into a multi-phase clock. Inputted random data are received by the sampling unit and sampled by the multi-phase clock. Each data bit of the random data is divided into several sampling intervals according to a phase number of the multi-phase clock. The digital logic unit analyses sampling values logically, judges the corresponding sampling interval of each sampling value and outputs signals for indicating that a frequency of the random data is higher or lower than the frequency of the single-phase clock based on differences in the corresponding sampling intervals of the sampling values at two adjacent times. A method for detecting frequencies is further provided.
摘要翻译：频率检测器包括多相时钟生成单元，连接到多相时钟生成单元的采样单元和连接到采样单元的数字逻辑单元。输入的单相时钟由多相时钟发生单元接收并变换为多相时钟。输入的随机数据由采样单元接收并由多相时钟采样。随机数据的每个数据位根据多相时钟的相位数被分成几个采样间隔。数字逻辑单元逻辑地分析采样值，判定每个采样值的相应采样间隔，并输出用于指示随机数据的频率高于或低于单相时钟频率的信号，基于相应采样的差异在两个相邻时间的采样值的间隔。还提供一种检测频率的方法。

34. 发明申请

US20120039427A1 Output signal adjustment system 有权
标题翻译：输出信号调节系统
公开(公告)号：US20120039427A1
公开(公告)日：2012-02-16
申请号：US13207310
申请日：2011-08-10
申请人： Zhaolei Wu , Guosheng Wu
发明人： Zhaolei Wu , Guosheng Wu
IPC分类号： H04L25/00
CPC分类号： H03K17/166 , H03K17/6871
摘要： An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.
摘要翻译：输出信号调整系统包括信号调整单元，基准斜率生成单元，斜率检测单元，电压 - 电流转换单元和控制单元。斜率检测单元将基准斜率生成单元的输出信号的上升沿和下降沿的斜率与信号调整单元的斜率进行比较，并输出电压信号。电压 - 电流转换单元将电压信号转换为电流信号。基于当前信号，控制单元将用于控制信号调节单元的调整的控制信号输出到输出信号的上升沿和下降沿的斜率。输出信号调节系统可以自动调整输出信号上升沿和下降沿的斜率，使输出信号对包装，印刷电路板，传输线等发送器负载不敏感。

35. 发明申请

US20120039381A1 Adaptive equalization system and method 有权
标题翻译：自适应均衡系统和方法
公开(公告)号：US20120039381A1
公开(公告)日：2012-02-16
申请号：US13196152
申请日：2011-08-02
申请人： Ziche Zhang , Guosheng Wu
发明人： Ziche Zhang , Guosheng Wu
IPC分类号： H04L27/01
CPC分类号： H04B3/145 , H04L25/03885
摘要： An adaptive equalization system includes an equalizer, a common-mode extraction buffer unit, a low-pass filter unit, a first and second energy compare units, a current comparator, and a digital control unit. The common-mode extraction buffer unit transmits a full spectral energy of an input signal received by the equalizer to the first energy compare unit and the low-pass filter unit, and extracts a common-mode signal of the input signal to the second energy compare unit. The first and second energy compare units respectively output a current signal characterized by the high-frequency energy and a current signal characterized by the low-frequency energy to the current comparator. Based on the compare result outputted by the current comparator, the digital control unit outputs an equalization control signal to the equalizer. The adaptive equalization system has the simple structure, and reduces the power consumption, the area and the manufacturing cost of the chip.
摘要翻译：自适应均衡系统包括均衡器，共模提取缓冲器单元，低通滤波器单元，第一和第二能量比较单元，电流比较器和数字控制单元。共模提取缓冲器单元将由均衡器接收的输入信号的全频谱能量发送到第一能量比较单元和低通滤波器单元，并将输入信号的共模信号提取到第二能量比较单元。第一和第二能量比较单元分别输出以高频能量为特征的电流信号和以电流比较器为特征的低频能量的电流信号。基于当前比较器输出的比较结果，数字控制单元向均衡器输出均衡控制信号。自适应均衡系统结构简单，降低了芯片的功耗，面积和制造成本。

36. 发明申请

US20120038395A1 Frequency multiplier system and method of multiplying frequency 有权
标题翻译：倍频系统和倍频方法
公开(公告)号：US20120038395A1
公开(公告)日：2012-02-16
申请号：US13208346
申请日：2011-08-12
申请人： Yong Quan , Guosheng Wu
发明人： Yong Quan , Guosheng Wu
IPC分类号： H03B19/00
CPC分类号： G06F1/08
摘要： A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N≧2, includes a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency. And a method of multiplying frequency is provided. The present invention does not need feedback circuits, and therefore is stable and fast-speed , saves area, and reduces energy consumption.
摘要翻译：一种倍频器系统，用于在处理输入时钟之后输出N倍频的单相时钟，N≥2，包括接收输入时钟的分频器，与分频器连接的内插器，与内插器连接的相位均衡器，以及与所述相位均衡器连接的组合逻辑电路，其中所述分频器将具有作为输入时钟的一半的两相频率的正交时钟输出到所述内插器，所述内插器将2N相时钟输出到所述相位均衡器，相位均衡器均匀化2N相时钟的相位偏移，组合逻辑电路将均匀化的2N相时钟合成为N倍频的单相时钟。并提供一种倍频方法。本发明不需要反馈电路，因此是稳定和快速的，节省了面积，并且降低了能量消耗。

37. 发明申请

US20100315149A1 High-speed data compared latch with auto-adjustment of offset 审中-公开
标题翻译：高速数据比较锁存器与自动调整偏移量
公开(公告)号：US20100315149A1
公开(公告)日：2010-12-16
申请号：US12797608
申请日：2010-06-10
申请人： Guosheng Wu , Bin Li
发明人： Guosheng Wu , Bin Li
IPC分类号： H03L5/00
CPC分类号： H03K3/356139
摘要： A high-speed data compared latch with auto-adjustment of offset, includes input pair transistors P, input pair transistors N, a compared latch module, an input control module, an output control module and a offset logic control module, the offset logic control module creates two control signals that regulate the number of input pair transistors P and input pair transistors N respectively according to reset signal RESET and the latched output of the compared latch module, and achieve self correcting of offset through regulating the number of the input pair transistors P and the input pair transistors N. The present invention is a feedback mechanism, automatically trimming the number of differential input pair to achieve the trimming differential pair operating point and the threshold voltage, eliminate the process variation, and latch on more precise control match the differential input pair transistors of the high-speed data compared latch in receiver accurately.
摘要翻译：具有自动调整偏移量的高速数据比较锁存器，包括输入对晶体管P，输入对晶体管N，比较锁存模块，输入控制模块，输出控制模块和偏移逻辑控制模块，偏移逻辑控制模块根据复位信号RESET和被锁存的比较锁存模块的输出产生分别调节输入对晶体管P和输入对晶体管N的数量的两个控制信号，并通过调节输入对晶体管的数量来实现偏移的自校正 P和输入对晶体管N.本发明是一种反馈机制，自动修整差分输入对的数量，以实现微调差分对工作点和阈值电压，消除过程变化，并锁定更精确的控制匹配差分输入对晶体管的高速数据比较锁存在接收机中的准确。

38. 发明授权

US07795942B2 Stage by stage delay current-summing slew rate controller 有权
公开(公告)号：US07795942B2
公开(公告)日：2010-09-14
申请号：US12475523
申请日：2009-05-31
申请人： Yong Quan , Guosheng Wu
发明人： Yong Quan , Guosheng Wu
IPC分类号： H03H11/26
CPC分类号： G05F3/16
摘要： A stage by stage delay current-summing slew rate controller includes a delay controller, a delay cell array, a current source array, a switch array, a load. The delay cell array includes N delay cells, the switch array includes N switches, and the switch includes N current sources, wherein N>1. The delay controller is connected with the control ports of the delay cells respectively, and the delay cells are connected with the control terminal of the switches respectively. One of the connecting terminals of the switch is connected with the output end of the current source, and the other end of the connecting terminals of the switch is connected with one end of the load, and the other end of the load is connected to the ground.

39. 发明申请

US20100052758A1 Stage by stage delay current-summing slew rate controller 有权
标题翻译：逐级延迟电流相加转换速率控制器
公开(公告)号：US20100052758A1
公开(公告)日：2010-03-04
申请号：US12475523
申请日：2009-05-31
申请人： Yong Quan , Guosheng Wu
发明人： Yong Quan , Guosheng Wu
IPC分类号： H03H11/26
CPC分类号： G05F3/16
摘要： A stage by stage delay current-summing slew rate controller includes a delay controller, a delay cell array, a current source array, a switch array, a load. The delay cell array includes N delay cells, the switch array includes N switches, and the switch includes N current sources, wherein N>1. The delay controller is connected with the control ports of the delay cells respectively, and the delay cells are connected with the control terminal of the switches respectively. One of the connecting terminals of the switch is connected with the output end of the current source, and the other end of the connecting terminals of the switch is connected with one end of the load, and the other end of the load is connected to the ground.
摘要翻译：逐级延迟电流求和转换速率控制器包括延迟控制器，延迟单元阵列，电流源阵列，开关阵列，负载。延迟单元阵列包括N个延迟单元，开关阵列包括N个开关，开关包括N个电流源，其中N> 1。延迟控制器分别与延迟单元的控制端口相连，延迟单元分别与开关的控制端相连。开关的一个连接端子与电流源的输出端连接，开关的连接端子的另一端与负载的一端连接，负载的另一端连接到地面。

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