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    • 31. 发明申请
    • Availability of space in a RISC microprocessor architecture
    • RISC微处理器架构中空间的可用性
    • US20070271441A1
    • 2007-11-22
    • US11881283
    • 2007-07-26
    • George ShawMartin McClurgBradley JensenRussell FishCharles Moore
    • George ShawMartin McClurgBradley JensenRussell FishCharles Moore
    • G06F15/00
    • G06F12/0875G06F9/30014G06F9/3005G06F9/30134G06F9/30145G06F9/30167G06F9/322G06F9/3824G06F9/3861G06F9/3877G06F9/3879G09G5/363G09G5/393G09G2360/121G09G2360/126
    • A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
    • 微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。 中央处理单元(CPU)指令集是硬连线的,允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动,从而提高性能。 微处理单元(MPU)包含52个通用寄存器,包括16个全局数据寄存器,一个索引寄存器,一个计数寄存器,一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。 两个堆栈都包含顶部元素中的索引寄存器,缓存在芯片上,并在需要时自动溢出并从外部存储器中重新填充。 堆栈最小化数据移动,并在过程调用,参数传递和变量赋值期间最小化存储器访问。 此外,MPU还包含一个模式/状态寄存器和41个用于I / O,控制,配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据,计数事件,测量时间和执行其他与时序相关的功能的输入输出处理器(IOP)。 零操作数堆栈架构消除了操作数位。 堆栈还可以在过程内和跨过程中最小化寄存器保存和加载,从而允许较短的指令序列和更快的运行代码。 指令简单易于解码和执行,允许MPU和IOP在单个时钟周期内发出和完成指令,每个时钟周期为100个本机MIPS峰值执行。 每次执行指令提取或预取时,CPU使用8位操作码,最多可从内存中获取四条指令。 这些指令可以重复,而不会从内存重新读取。 当直接连接到DRAM而没有高速缓存时,这将保持高性能。
    • 32. 发明授权
    • Mobile load handling or lifting machines
    • 移动式装载机或起重机械
    • US3670910A
    • 1972-06-20
    • US3670910D
    • 1970-07-23
    • DONALD GEORGE SHAWSHAW TREW & SMITH LTD
    • SHAW DONALD GEORGE
    • B66F9/065E02F3/34E02F9/02E02F9/08E02F3/00
    • E02F9/0808B66F9/0655E02F3/3411E02F9/02
    • A mobile machine for load handling or lifting purposes is disclosed in which an attachment head, for receiving load handling means attached to it, is carried for raising and lowering movement by forwardly extending parallel motion linkage pivotally connected to a forwardly extendible and rearwardly retractable member of a telescopic boom longitudinally carried by an extendible wheeled chassis of the machine, the boom being also arranged to be bodily advanced or retracted relative to the chassis by support linkage which is linked to the chassis for fore and aft extension of the latter to counteract the machine against forward tipping movement on such bodily advance of the telescopic boom.
    • 公开了一种用于负载处理或提升目的的移动机器,其中承载用于接收负载处理装置的附接头,用于通过向前延伸的平行运动连杆进行升降运动,所述平行运动连杆枢转地连接到可向前伸展和向后伸缩的构件 由机器的可延伸的轮式底盘纵向承载的伸缩式起重臂,悬臂还布置成通过支撑联动装置相对于底盘而被身体前进或缩回,该联动装置连接到底盘,用于前者的后部和后部延伸以抵抗机器 在伸缩臂的这种身体前进方向上的向前倾斜运动。
    • 38. 发明授权
    • Mobile load-lifting machines
    • 移动式起重机
    • US3633702A
    • 1972-01-11
    • US3633702D
    • 1969-10-31
    • SHAW TREW & SMITH LTDDONALD GEORGE SHAW
    • SHAW DONALD GEORGE
    • B62D7/02B66C23/62B62D5/06
    • B66C23/62B62D7/02
    • In a mobile load-lifting machine such as a wheeled crane in which the front and rear pairs of wheels are arranged for relative extension and retraction in accordance with the loadhandling position of the machine or crane and in which at least one pair of wheels such as the front pair are inturnable for load-slewing movement of the machine, the provision of means for ensuring appropriate inturning of said pair of wheels according to the extended or retracted position of the front and rear wheels and which consists of a movable member linked to the pivotal mounting of the inturnable wheels and cooperating with a stop member which latter is adjustable in accordance with the wheel extension and retraction for permitting corresponding variation in the extent of movement of the movable member and hence of inturning movement of the inturnable pair of wheels.
    • 在诸如轮式起重机的移动式起重机中,其中前轮对和后轮对被布置成根据机器或起重机的负载处理位置进行相对的延伸和缩回,并且其中至少一对轮 例如前部对可以用于机器的负载回转运动,提供用于根据前轮和后轮的延伸或缩回位置确保所述一对车轮适当地转动的装置,并且由可动件连接 到可转动的轮的枢转安装并且与止动构件配合,止挡构件可根据车轮延伸和缩回来调节,以允许可移动构件的运动程度的相应变化,并且因此允许可转动的一对车轮的转动 。