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31. 发明申请

US20090249039A1 Providing Extended Precision in SIMD Vector Arithmetic Operations 有权
标题翻译：在SIMD矢量算术运算中提供扩展精度
公开(公告)号：US20090249039A1
公开(公告)日：2009-10-01
申请号：US12480414
申请日：2009-06-08
申请人： Timothy Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行的结果元素写入累加器。然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

32. 发明授权

US07546443B2 Providing extended precision in SIMD vector arithmetic operations 有权
标题翻译：提供SIMD向量算术运算中的扩展精度
公开(公告)号：US07546443B2
公开(公告)日：2009-06-09
申请号：US11337440
申请日：2006-01-24
申请人： Timothy J. Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy J. Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行的结果元素写入累加器。然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

33. 发明申请

US20080244471A1 SYSTEM AND METHOD OF CUSTOMIZING AN EXISTING PROCESSOR DESIGN HAVING AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE WITH INSTRUCTION EXTENSIONS 有权
标题翻译：现有处理器设计的系统和方法，具有指令扩展的现有处理器指令集架构
公开(公告)号：US20080244471A1
公开(公告)日：2008-10-02
申请号：US12135563
申请日：2008-06-09
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
摘要翻译：自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

34. 发明授权

US06477683B1 Automated processor generation system for designing a configurable processor and method for the same 有权
标题翻译：用于设计可配置处理器的自动处理器生成系统及其方法
公开(公告)号：US06477683B1
公开(公告)日：2002-11-05
申请号：US09246047
申请日：1999-02-05
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
摘要翻译：自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

35. 发明授权

US06282633B1 High data density RISC processor 有权
标题翻译：高数据密度RISC处理器
公开(公告)号：US06282633B1
公开(公告)日：2001-08-28
申请号：US09192395
申请日：1998-11-13
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson
IPC分类号： G06K930
CPC分类号： G06F9/30178 , G06F9/30145 , G06F9/30167
摘要： A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S=IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load/store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.
摘要翻译： RISC处理器实现指令集，除了优化执行程序所需的指令数，时钟周期和每个指令的平均时钟数之间的关系外，还设计用于优化方程S = IS * BI，其中S是以位为单位的程序指令的大小，IS是表示程序所需的指令的静态数量（而不是执行所需的数目），BI是每个指令的平均位数。与传统的RISC体系结构相比，该处理器降低了BI和IS，时钟周期和每个指令的平均时钟周期几乎没有增加。处理器在基于RISC原理的固定长度高性能编码中提供了良好的代码密度，包括具有加载/存储架构的通用寄存器。此外，处理器实现了保持高性能的简单可变长度编码。

36. 发明授权

US6092187A Instruction prediction based on filtering 失效
公开(公告)号：US6092187A
公开(公告)日：2000-07-18
申请号：US935369
申请日：1997-09-22
申请人： Earl A. Killian
发明人： Earl A. Killian
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： Instruction prediction based upon confidence and priority levels. A filtering effect is achieved by providing for prediction of an instruction by one of a plurality of predictors having (1) a confidence level satisfying a predetermined threshold value and (2) the highest priority level among the plurality of predictors. A default predictor is provided should no predictor satisfy this criteria. Efficient use of predictor memory is achieved through selective updating of predictors.

37. 发明授权

US5864703A Method for providing extended precision in SIMD vector arithmetic operations 失效
标题翻译：在SIMD向量算术运算中提供扩展精度的方法
公开(公告)号：US5864703A
公开(公告)日：1999-01-26
申请号：US947648
申请日：1997-10-09
申请人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F9/30 , G06F9/302 , G06F15/78 , G06F15/76
CPC分类号： G06F9/30014 , G06F15/8084 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一向量寄存器和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。然后，本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行结果写入累加器。然后，累加器中的每个元素被变换成N位元素并存储到存储器中。

38. 发明授权

US5568630A Backward-compatible computer architecture with extended word size and address space 失效
公开(公告)号：US5568630A
公开(公告)日：1996-10-22
申请号：US391946
申请日：1995-02-21
申请人： Earl A. Killian , Thomas J. Riordan , Danny L. Freitas , Ashish B. Dixit , John L. Hennessy
发明人： Earl A. Killian , Thomas J. Riordan , Danny L. Freitas , Ashish B. Dixit , John L. Hennessy
IPC分类号： G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/355 , G06F12/02 , G06F12/06
CPC分类号： G06F9/342 , G06F9/30014 , G06F9/30036 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/30192 , G06F9/324
摘要： A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths. The extended architecture supports the m-bit architecture's addressing with minimal additional hardware. This is made possible by storing m-bit addresses as N-bit entities in sign-extended form and requiring that the results of address computations on these entities be in sign-extended form.

39. 发明授权

US5420992A Backward-compatible computer architecture with extended word size and address space 失效
标题翻译：具有扩展字长和地址空间的向后兼容的计算机体系结构
公开(公告)号：US5420992A
公开(公告)日：1995-05-30
申请号：US223388
申请日：1994-04-05
申请人： Earl A. Killian , Thomas J. Riordan , Danny L. Freitas , Ashish B. Dixit , John L. Hennessy
发明人： Earl A. Killian , Thomas J. Riordan , Danny L. Freitas , Ashish B. Dixit , John L. Hennessy
IPC分类号： G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/355 , G06F12/02 , G06F12/10
CPC分类号： G06F9/342 , G06F9/30014 , G06F9/30036 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/30192 , G06F9/324
摘要： A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths. The extended architecture supports the m-bit architecture's addressing with minimal additional hardware. This is made possible by storing m-bit addresses as N-bit entities in sign-extended form and requiring that the results of address computations on these entities be in sign-extended form.
摘要翻译：用于扩展预先存在的架构的数据字大小和虚拟地址空间的技术，使得用于扩展架构的硬件也支持预先存在的架构。将数据字大小从m位扩展到N位需要将机器寄存器和数据路径从m位扩展到N位，并将m个或更少位的符号扩展实体加载到寄存器中，将其扩展为N位。当在m位实体的N位签名扩展版本上运行时，一些m位指令产生可能与正确的m位结果不符的N位结果，符号扩展到N位。对于这些说明，兼容性要求进一步定义说明以保证符号扩展结果。这意味着需要与这些m位指令相对应的单独的N位指令。部分地通过扩展虚拟地址数据路径来提供对N位虚拟地址空间的支持。扩展架构通过最少的额外硬件支持m位架构的寻址。这可以通过将m位地址存储为符号扩展形式的N位实体，并要求对这些实体的地址计算结果进行符号扩展。

40. 发明授权

US5027270A Processor controlled interface with instruction streaming 失效
标题翻译：处理器控制接口，带指令流
公开(公告)号：US5027270A
公开(公告)日：1991-06-25
申请号：US255791
申请日：1988-10-11
申请人： Thomas J. Riordan , Paul S. Ries , Edwin L. Hudson , Earl A. Killian
发明人： Thomas J. Riordan , Paul S. Ries , Edwin L. Hudson , Earl A. Killian
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F12/0859 , G06F9/3802
摘要： A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.
摘要翻译：处理器，指令高速缓存和主存储器之间的处理器控制的接口提供用于从主存储器中的指令块同时重新填充高速缓存并且在块被写入高速缓存时处理该块中的指令。

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