专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07795063B2 Micro-electro-mechanical systems (MEMS) device and process for fabricating the same 有权
标题翻译：微电子机械系统（MEMS）装置及其制造方法
公开(公告)号：US07795063B2
公开(公告)日：2010-09-14
申请号：US11967261
申请日：2007-12-31
申请人： Tsung-Min Hsieh , Chien-Hsing Lee
发明人： Tsung-Min Hsieh , Chien-Hsing Lee
IPC分类号： H01L21/00 , H01L29/78 , H04R25/00 , H04R11/02
CPC分类号： B81C1/00182 , B81C1/00246 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
摘要： A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural dielectric layer. A second structural dielectric layer, formed over the back-plate substrate. The etching stop layer and the second structural dielectric layer form at least a part of a micro-machine diaphragm, and cover over the opening of the first structural dielectric layer to form a chamber between the micro-machine diaphragm and the back-plate substrate.
摘要翻译：微电子机械系统（MEMS）装置包括背板基板，其具有形成有多个穿孔的预期区域。布置在所述背板基板上的第一结构介电层，其中所述电介质层具有在所述预定区域上方的开口。设置在第一结构介电层上的蚀刻停止层。形成在背板基板上的第二结构介电层。蚀刻停止层和第二结构介电层形成微机隔膜的至少一部分，并且覆盖在第一结构介电层的开口上，以在微机隔膜和背板基板之间形成室。

32. 发明申请

US20080197351A1 TESTKEY DESIGN PATTERN FOR GATE OXIDE 有权
标题翻译：用于氧化铝的试验设计图案
公开(公告)号：US20080197351A1
公开(公告)日：2008-08-21
申请号：US11675635
申请日：2007-02-16
申请人： Shyh-Fann Ting , Sheng-Hao Lin , Chien-Hsing Lee , Da- Ching Chiou , Sun-Chin Wei , Min-Yi Chang , Cheng-Tung Huang , Tung-Hsing Lee , Tzyy-Ming Cheng
发明人： Shyh-Fann Ting , Sheng-Hao Lin , Chien-Hsing Lee , Da- Ching Chiou , Sun-Chin Wei , Min-Yi Chang , Cheng-Tung Huang , Tung-Hsing Lee , Tzyy-Ming Cheng
IPC分类号： H01L23/58
CPC分类号： H01L22/34
摘要： A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.
摘要翻译：测试键设计模式包括至少一个导电触点，垂直并电连接到导电触点的至少一个第一宽度的导线和分别直接连接到导线的每一侧的至少一对源极和漏极。一对源极和漏极以及直接连接到源极和漏极的第一长度的导电线的一部分形成电子器件。测试键设计模式在测量电容时具有较小误差和更好的栅极氧化物厚度提取的优势。

33. 发明授权

US07061042B2 Double-cell memory device 有权
标题翻译：双电池存储器件
公开(公告)号：US07061042B2
公开(公告)日：2006-06-13
申请号：US10871170
申请日：2004-06-18
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7923
摘要： A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.
摘要翻译：存储器阵列器件具有多个栅极结构线，沿着一个方向相邻地设置在衬底上，其中栅极结构线的至少一部分具有记忆功能。多个第一掺杂区域，在栅极结构线的第一条线的一侧的衬底中。在栅极结构线的最后一行的一侧的衬底中的多个第二掺杂区域。其中第一掺杂区和第二掺杂区相对于多个位线分别用于多对掺杂区。换句话说，每个存储单元的常规源/漏区被保存。相反，栅极线相邻地放置在一起。

34. 发明申请

US20060007724A1 Double-cell memory device 审中-公开
公开(公告)号：US20060007724A1
公开(公告)日：2006-01-12
申请号：US11222377
申请日：2005-09-07
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C17/00
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7923
摘要： A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.

35. 发明申请

US20050224865A1 CIRCUIT LAYOUT AND STRUCTURE FOR A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的电路布局和结构
公开(公告)号：US20050224865A1
公开(公告)日：2005-10-13
申请号：US10823488
申请日：2004-04-12
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C11/34 , G11C16/04 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/42328 , H01L29/42344 , H01L29/7887 , H01L29/7923
摘要： A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.
摘要翻译：非易失性存储器的结构包含衬底。沿着第一方向在衬底中形成多个位线，其中每个位线还用作源极/漏极（S / D）区域。第一电介质层设置在衬底上。在位线之间的第一电介质层上形成多个选择栅（SG）线。在位线和SG线之间的衬底上形成多个电荷存储结构层。在SG线上形成第二电介质层，并且在位线之上形成第三介电层。沿着与位线的第一方向交叉的第二方向在基板上形成多个字线。其中，当所选择的一条SG线施加电压时，在所选择的一条SG线之下的衬底中产生另一S / D区。

36. 发明申请

US20050170588A1 Method for forming multi-level mask ROM cell and NAND multi-level mask ROM 有权
标题翻译：用于形成多电平掩模ROM单元和NAND多级掩模ROM的方法
公开(公告)号：US20050170588A1
公开(公告)日：2005-08-04
申请号：US10886981
申请日：2004-07-07
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C11/56 , H01L21/8234 , H01L21/8246 , H01L27/112
CPC分类号： G11C11/5692 , G11C16/0483 , H01L27/112 , H01L27/1122 , H01L27/1126
摘要： The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing the data storage capacity.
摘要翻译：本发明涉及可存储两位的多级只读存储器单元及其制造方法。多级ROM单元具有两位的存储容量，并且所得的NAND型ROM存储器阵列可以提供两位的四个逻辑状态，从而增加数据存储容量。

37. 发明授权

US06242309B1 Method of forming a split gate flash memory cell 失效
标题翻译：形成分裂栅极闪存单元的方法
公开(公告)号：US06242309B1
公开(公告)日：2001-06-05
申请号：US09584696
申请日：2000-06-01
申请人： Chien-Hsing Lee
发明人： Chien-Hsing Lee
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： A semiconductor wafer includes a silicon substrate, at least two floating gates positioned on the silicon substrate and a silicon nitride layer positioned on the surface of each floating gate. The method first uses a lithographic process and an ion implantation process to form a drain in the silicon substrate between the two floating gates. A passivation layer is then formed uniformly on the surface of the silicon substrate and the top surface and the sides of the floating gate. An etching process is performed later to form a spacer around each floating gate, the spacers between the floating gate are joined and cover the drain. Finally, an ion implantation process is performed, using the spacers as a hard mask, to form a source in the silicon substrate.
摘要翻译：半导体晶片包括硅衬底，位于硅衬底上的至少两个浮置栅极和位于每个浮置栅极表面上的氮化硅层。该方法首先使用光刻工艺和离子注入工艺在两个浮栅之间的硅衬底中形成漏极。然后在硅衬底的表面和浮动栅极的顶表面和侧面上均匀地形成钝化层。稍后进行蚀刻处理以在每个浮动栅极周围形成间隔物，浮置栅极之间的间隔物接合并覆盖漏极。最后，使用间隔物作为硬掩模进行离子注入工艺，以在硅衬底中形成源。

38. 发明授权

US08258591B2 Micro-electro-mechanical systems (MEMS) device 有权
标题翻译：微机电系统（MEMS）装置
公开(公告)号：US08258591B2
公开(公告)日：2012-09-04
申请号：US12014810
申请日：2008-01-16
申请人： Chien-Hsing Lee , Tsung-Min Hsieh
发明人： Chien-Hsing Lee , Tsung-Min Hsieh
IPC分类号： H01L29/84
CPC分类号： B81C1/00246 , B81B2201/0235 , B81B2201/0242 , B81B2201/0257 , B81C2201/014 , B81C2203/0714 , B81C2203/0735
摘要： The present invention provides a MEMS device, be implemented on many MEMS device, such as MEMS microphone, MEMS speaker, MEMS accelerometer, MEMS gyroscope. The MEMS device includes a substrate. A dielectric structural layer is disposed over the substrate, wherein the dielectric structural layer has an opening to expose the substrate. A diaphragm layer is disposed over the dielectric structural layer, wherein the diaphragm layer covers the opening of the dielectric structural layer to form a chamber. A conductive electrode structure is adapted in the diaphragm layer and the substrate to store nonvolatile charges.
摘要翻译：本发明提供了一种MEMS器件，可在诸如MEMS麦克风，MEMS扬声器，MEMS加速度计，MEMS陀螺仪的许多MEMS器件上实现。 MEMS器件包括衬底。电介质结构层设置在衬底上，其中电介质结构层具有露出衬底的开口。隔膜层设置在电介质结构层上，其中隔膜层覆盖电介质结构层的开口以形成室。导电电极结构适用于隔膜层和基板以存储非易失性电荷。

39. 发明授权

US08217474B2 Hermetic MEMS device and method for fabricating hermetic MEMS device and package structure of MEMS device 有权
标题翻译：用于制造MEMS器件的密封MEMS器件和封装结构的密封MEMS器件和方法
公开(公告)号：US08217474B2
公开(公告)日：2012-07-10
申请号：US12647559
申请日：2009-12-28
申请人： Chien-Hsing Lee , Tsung-Min Hsieh , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Tsung-Min Hsieh , Jhyy-Cheng Liou
IPC分类号： H01L27/14
CPC分类号： B81C1/00246 , B81B7/0064 , B81B2207/015 , B81B2207/07 , B81B2207/092 , B81C2203/0714 , H01L2224/48091 , H01L2224/48247 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A hermetic microelectromechanical system (MEMS) package includes a CMOS MEMS chip and a second substrate. The CMOS MEMS Chip has a first substrate, a structural dielectric layer, a CMOS circuit and a MEMS structure. The structural dielectric layer is disposed on a first side of the first structural substrate. The structural dielectric layer has an interconnect structure for electrical interconnection and also has a protection structure layer. The first structural substrate has at least a hole. The hole is under the protection structure layer to form at least a chamber. The chamber is exposed to the environment in the second side of the first structural substrate. The chamber also comprises a MEMS structure. The second substrate is adhered to a second side of the first substrate over the chamber to form a hermetic space and the MEMS structure is within the space.
摘要翻译：密封微机电系统（MEMS）封装包括CMOS MEMS芯片和第二基板。 CMOS MEMS芯片具有第一衬底，结构介电层，CMOS电路和MEMS结构。结构介电层设置在第一结构基板的第一侧上。结构介电层具有用于电互连的互连结构，并且还具有保护结构层。第一结构基底具有至少一个孔。该孔位于保护结构层之下，以形成至少一个腔室。该室暴露于第一结构基板的第二侧的环境。该腔室还包括MEMS结构。第二衬底在室上粘附到第一衬底的第二侧以形成密封空间，并且MEMS结构在空间内。

40. 发明授权

US08173471B2 Method for fabricating micro-electro-mechanical system (MEMS) device 有权
标题翻译：微机电系统（MEMS）装置的制造方法
公开(公告)号：US08173471B2
公开(公告)日：2012-05-08
申请号：US12111208
申请日：2008-04-29
申请人： Tsung-Min Hsieh , Chien-Hsing Lee
发明人： Tsung-Min Hsieh , Chien-Hsing Lee
IPC分类号： H01L21/00 , H01L29/84
CPC分类号： B81C1/00246 , B81B2201/0235 , B81B2207/015 , B81C2203/0714 , B81C2203/0735 , G01P15/0802 , G01P15/125
摘要： A method for fabricating MEMS device includes providing a substrate having a first side and a second side. Then, a structural dielectric layer is formed over the substrate at the first side, wherein a structural conductive layer is embedded in the structural dielectric layer. A multi-stage patterning process is performed on the substrate from the second side, wherein a plurality of regions of the substrate with different levels is formed and a portion of the structural dielectric layer is exposed. An isotropic etching process is performed from the second side of the substrate or from the both side of the substrate to etch the structural dielectric layer, wherein a remaining portion of the structural dielectric layer comprises the structural conductive layer and a dielectric portion enclosed by the structural conductive layer.
摘要翻译：一种用于制造MEMS器件的方法包括提供具有第一侧和第二侧的衬底。然后，在第一侧的基板上形成结构介电层，其中结构导电层嵌入结构介电层中。从第二侧在基板上进行多级图案化处理，其中形成具有不同层次的基板的多个区域，并且结构介电层的一部分被暴露。从衬底的第二侧或从衬底的两侧进行各向同性蚀刻工艺，以蚀刻结构电介质层，其中结构介电层的剩余部分包括结构导电层和由结构介电层包围的电介质部分导电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式