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31. 发明申请

US20080030894A1 SERVO WRITING WITH OFFSET COMPENSATION FOR PREWRITTEN REFERENCE 有权
标题翻译： SERVO写入偏移补偿用于PREWRITTEN参考
公开(公告)号：US20080030894A1
公开(公告)日：2008-02-07
申请号：US11740747
申请日：2007-04-26
申请人： YU SUN , Dave McMurtrey , Bruce Liikanen , Don Brunnett , John VanLaanen , Charles Watt , Stanley Shepherd , S. Smith , Todd Franks , Lin Guo
发明人： YU SUN , Dave McMurtrey , Bruce Liikanen , Don Brunnett , John VanLaanen , Charles Watt , Stanley Shepherd , S. Smith , Todd Franks , Lin Guo
IPC分类号： G11B17/08
CPC分类号： G11B25/043 , G11B5/59627 , G11B5/59661 , G11B5/59666
摘要： In accordance with various embodiments, a rotatable member is mounted to a spindle hub so that initial servo data previously provided to the rotatable member are eccentrically offset with respect to a rotational center of the spindle hub. Compensation vales are determined to characterize said offset, after which final servo data are provided to the rotatable member in relation to the initial servo data and the determined compensation values. The final servo data are nominally concentric with the rotational center of the spindle hub.
摘要翻译：根据各种实施例，可旋转构件安装到主轴毂，使得先前提供给可旋转构件的初始伺服数据相对于主轴毂的旋转中心偏心偏移。确定补偿值以表征所述偏移，之后相对于初始伺服数据和确定的补偿值将最终伺服数据提供给可旋转构件。最终伺服数据名义上与主轴毂的旋转中心同心。

32. 发明授权

US07185159B2 Technique for accessing memory in a data processing apparatus 有权
标题翻译：用于访问数据处理设备中的存储器的技术
公开(公告)号：US07185159B2
公开(公告)日：2007-02-27
申请号：US10714520
申请日：2003-11-17
申请人： Lionel Beinet , David Hennah Mansell , Simon Charles Watt
发明人： Lionel Beinet , David Hennah Mansell , Simon Charles Watt
IPC分类号： G06F12/00
CPC分类号： G06F21/85 , G06F12/1491 , G06F21/629 , G06F21/74 , G06F2221/2105 , G06F2221/2141 , G06F2221/2149
摘要： The present invention provides a data processing apparatus and method for accessing memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled via a device bus with the memory, the device being operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the invention, the memory access request as issued by the device includes a domain signal identifying whether the memory access request pertains to either the secure domain or the non-secure domain. The presence of this domain signal issued as part of the memory access request enables checking to be performed to ensure that secure data within the secure memory is not accessed by the device when the memory access request pertains to the non-secure domain.
摘要翻译：本发明提供一种访问存储器的数据处理装置和方法。数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。数据处理设备包括经由设备总线与存储器耦合的设备，当设备需要存储器中的数据项时，该设备可操作地向设备总线发出与安全性相关的存储器访问请求域或非安全域。存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。根据本发明，由设备发布的存储器访问请求包括识别存储器访问请求是否属于安全域或非安全域的域信号。作为存储器访问请求的一部分而发布的该域信号的存在使得能够执行检查，以便当存储器访问请求与非安全域相关时，确保安全存储器内的安全数据不被设备访问。

33. 发明授权

US5875465A Cache control circuit having a pseudo random address generator 失效
标题翻译：高速缓存控制电路具有伪随机地址发生器
公开(公告)号：US5875465A
公开(公告)日：1999-02-23
申请号：US832091
申请日：1997-04-03
申请人： Michael Thomas Kilpatrick , Simon Charles Watt , Guy Larri
发明人： Michael Thomas Kilpatrick , Simon Charles Watt , Guy Larri
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/128 , G06F12/0848 , G06F12/126
摘要： A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.
摘要翻译：一种包含高速缓冲存储器2和中央处理单元的数据处理系统。存储控制电路10响应于可编程分区设置PartVal，以根据中央处理单元4是否用信号I / D指示要存储在高速缓存存储器2中的单词来指示高速缓存在指令字和数据字之间由指令字缓存未命中或数据字高速缓存未命中引起。缓存存储器阵列2可以具有可编程尺寸的部分锁定，使得它不被替换。在进行重写的互补可编程范围内的选择使用伪随机数选择技术，该伪随机数生成器以线性反馈移位寄存器的形式触发递增计数器。

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