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31. 发明授权

US06087225A Method for dual gate oxide dual workfunction CMOS 失效
标题翻译：双栅氧化双功函数CMOS方法
公开(公告)号：US06087225A
公开(公告)日：2000-07-11
申请号：US18939
申请日：1998-02-05
申请人： Gary Bela Bronner , Badih El-Kareh , Stanley Everett Schuster
发明人： Gary Bela Bronner , Badih El-Kareh , Stanley Everett Schuster
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10873 , H01L21/823842
摘要： A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO.sub.2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.
摘要翻译：在同一芯片上形成包括两个不同类型的NFET和/或两个不同类型的PFET的集成电路芯片的方法，例如厚和薄栅极氧化物FET。 DRAM阵列可以由厚氧化物FET构成，并且逻辑电路可以由同一芯片上的薄氧化物FET构成。首先，在晶片上形成包括第一厚栅极SiO 2层的栅极堆叠。堆叠包括栅极氧化物层上的掺杂多晶硅层，多晶硅层上的硅化物层和硅化物层上的氮化物层。选择性地去除堆叠的一部分以重新暴露将要形成逻辑电路的晶片。在再曝光的晶片上形成更薄的栅氧化层。接下来，在较薄的栅极氧化物层上形成栅极，并且在栅极处形成薄氧化物NFET和PFET。在选择性硅化薄氧化物器件区域之后，在厚氧化物器件区域中从堆叠中蚀刻栅极。最后，源极和漏极区域被注入并扩散用于厚栅极氧化物器件。

32. 发明授权

US5889410A Floating gate interlevel defect monitor and method 失效
标题翻译：浮栅层间缺陷监测和方法
公开(公告)号：US5889410A
公开(公告)日：1999-03-30
申请号：US652216
申请日：1996-05-22
申请人： Badih El-Kareh , Stephen Parke
发明人： Badih El-Kareh , Stephen Parke
IPC分类号： H01L23/544 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002
摘要： According to the preferred embodiment, a defect monitor is provided that uses a floating gate structure. The defect monitor includes a common source, a common drain, and a plurality of floating gates interdispersed between the source and drain. Additionally, a conductor covers the plurality of floating gates. By applying a bias to the conductor and measuring the current flowing through the drain and source, the distribution of defects on the semiconductor wafer can be estimated.
摘要翻译：根据优选实施例，提供了使用浮动栅极结构的缺陷监视器。缺陷监视器包括公共源，公共漏极和分散在源极和漏极之间的多个浮动栅极。另外，导体覆盖多个浮动栅极。通过向导体施加偏压并测量流过漏极和源极的电流，可以估计半导体晶片上的缺陷分布。

33. 发明授权

US5805494A Trench capacitor structures 失效
公开(公告)号：US5805494A
公开(公告)日：1998-09-08
申请号：US846603
申请日：1997-04-30
申请人： Badih El-Kareh , Richard Leo Kleinhenz , Stanley Everett Schuster
发明人： Badih El-Kareh , Richard Leo Kleinhenz , Stanley Everett Schuster
IPC分类号： H01L27/108 , H01L27/11 , H01L29/94 , G11C11/24
CPC分类号： H01L29/945 , H01L27/10829 , H01L27/1104 , Y10S257/903
摘要： An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit. An outer plate of the capacitor in the form of an out diffusion from the trench provides a low resistance electrical contact with the substrate. A number of these capacitors can be combined in a very efficient X-Y array of decoupling capacitors.

34. 发明授权

US5763918A ESD structure that employs a schottky-barrier to reduce the likelihood of latch-up 失效
标题翻译：使用肖特基势垒的ESD结构减少闭锁的可能性
公开(公告)号：US5763918A
公开(公告)日：1998-06-09
申请号：US740134
申请日：1996-10-22
申请人： Badih El-Kareh , James Gardner Ryan , Hiroyoshi Tanimoto
发明人： Badih El-Kareh , James Gardner Ryan , Hiroyoshi Tanimoto
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/092 , H01L29/47 , H01L29/872 , H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.
摘要翻译：本发明的优选实施例克服了现有技术的局限，并且提供了一种通过抑制引起晶体管作用发生的少数载流子的注入来减小ESD结构的闭锁敏感性的装置和方法。这是通过例如通过使用与n衬底或n阱的金属接触来代替或与现有技术的p-扩散并行来实现的。使用这种金属接触形成具有ESD结构的肖特基势垒二极管（SBD）。由于SBD是多数载波器件，当SBD处于正向偏置时，可以忽略少数载流子，从而降低闩锁的可能性。

35. 发明授权

US5708559A Precision analog metal-metal capacitor 失效
公开(公告)号：US5708559A
公开(公告)日：1998-01-13
申请号：US549450
申请日：1995-10-27
申请人： Terry J. Brabazon , Badih El-Kareh , Stuart R. Martin , Matthew J. Rutten , Carter W. Kaanta
发明人： Terry J. Brabazon , Badih El-Kareh , Stuart R. Martin , Matthew J. Rutten , Carter W. Kaanta
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L21/822 , H01G4/20 , H01G4/06
CPC分类号： H01L28/40 , H01L21/76895
摘要： A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

36. 发明授权

US08847359B2 High voltage bipolar transistor and method of fabrication 有权
标题翻译：高压双极晶体管及其制造方法
公开(公告)号：US08847359B2
公开(公告)日：2014-09-30
申请号：US12537246
申请日：2009-08-06
申请人： Scott Gerard Balster , Hiroshi Yasuda , Philipp Steinmann , Badih El-Kareh
发明人： Scott Gerard Balster , Hiroshi Yasuda , Philipp Steinmann , Badih El-Kareh
IPC分类号： H01L21/331 , H01L29/73 , H01L29/66 , H01L21/762 , H01L29/737 , H01L29/732 , H01L29/161 , H01L29/10
CPC分类号： H01L29/7378 , H01L21/76283 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/732
摘要： High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
摘要翻译：由于Kirk效应，用BiCMOS工艺制造的高电压双极型晶体管在高电流密度下表现出减小的增益。 Kirk效应开始的阈值电流密度由于高电压操作所需的较低掺杂密度而降低。由于Kirk效应，在高集电极电流密度下扩大的基极区域横向扩展到具有高密度复合位点的区域，导致基极电流增加和增益下降。本发明在IC中提供了具有不显着增加基极 - 发射极电容的构造中的扩展的非硅化基极外部区域的双极晶体管。可以使用硅化物阻挡层或发射极 - 基极介电层的延伸区域来实现基极外部区域的横向延伸。还公开了利用本发明的双极晶体管制造IC的方法。

37. 发明授权

US08530952B2 Systems, methods and devices for a memory having a buried select line 有权
标题翻译：具有掩埋选择线的存储器的系统，方法和装置
公开(公告)号：US08530952B2
公开(公告)日：2013-09-10
申请号：US11895505
申请日：2007-08-23
申请人： Badih El-Kareh
发明人： Badih El-Kareh
IPC分类号： H01L29/788
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/0416 , G11C16/06 , G11C16/26 , H01L27/11521 , H01L27/11524
摘要： Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.
摘要翻译：描述了通过利用掩埋选择线来编程和擦除存储器单元的存储单元和方法。可以在源极 - 漏极区域和存储单元的掩埋选择线区域之间产生电压电位，以将电荷存储在源极 - 漏极和埋入选择线区域之间的存储区域中。所产生的电压电位导致电子向掩埋的存储区域隧道以存储电荷或远离掩埋的存储区域以放电电荷。

38. 发明授权

US08502280B2 Fin-JFET 有权
公开(公告)号：US08502280B2
公开(公告)日：2013-08-06
申请号：US13086246
申请日：2011-04-13
申请人： Badih El-Kareh , Leonard Forbes
发明人： Badih El-Kareh , Leonard Forbes
IPC分类号： H01L29/66
CPC分类号： H01L27/0617 , H01L21/8232 , H01L21/845 , H01L27/085 , H01L27/0922 , H01L27/098 , H01L27/1211 , H01L29/66795 , H01L29/7832 , H01L29/785 , H01L29/8086
摘要： Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

39. 发明授权

US08294218B2 Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权
标题翻译：具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路
公开(公告)号：US08294218B2
公开(公告)日：2012-10-23
申请号：US12796386
申请日：2010-06-08
申请人： Badih El-Kareh , Scott Gerard Balster , Hiroshi Yasuda , Manfred Schiekofer
发明人： Badih El-Kareh , Scott Gerard Balster , Hiroshi Yasuda , Manfred Schiekofer
IPC分类号： H01L27/06
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0251 , H01L27/0705
摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
摘要翻译：具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接结构体。形成身体接触结构的基层也形成双极器件的基部。本发明还涉及一种用于制造这种集成电路的方法。

40. 发明授权

US08012844B2 Method of manufacturing an integrated circuit 有权
标题翻译：集成电路的制造方法
公开(公告)号：US08012844B2
公开(公告)日：2011-09-06
申请号：US12624442
申请日：2009-11-24
申请人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
发明人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
IPC分类号： H01L21/20
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area.
摘要翻译：一种制造集成电路的方法包括沉积用作薄膜电阻器（TFR）的材料的电阻层，在电阻层上沉积电绝缘层，从电离层的电活性区域外部去除电绝缘层对应于目标TFR区域的电阻层，以及沉积导电材料的导电层，使得导电层与靶TFR区域重叠，导电层与目标TFR区域外的电阻层电接触。

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