专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20090085042A1 Display device having thin film semiconductor device and manufacturing method of thin film semiconductor device 有权
标题翻译：具有薄膜半导体器件的显示器件和薄膜半导体器件的制造方法
公开(公告)号：US20090085042A1
公开(公告)日：2009-04-02
申请号：US12219837
申请日：2008-07-29
申请人： Toshiyuki Mine , Mitsuharu Tai , Akio Shima
发明人： Toshiyuki Mine , Mitsuharu Tai , Akio Shima
IPC分类号： H01L21/20 , H01L29/04
CPC分类号： H01L21/268 , H01L21/02529 , H01L21/02532 , H01L21/02667 , H01L21/02675 , H01L21/02686 , H01L27/1285 , H01L29/78642
摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.
摘要翻译：一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体，半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。

32. 发明授权

US07098111B2 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07098111B2
公开(公告)日：2006-08-29
申请号：US10948142
申请日：2004-09-24
申请人： Akio Shima
发明人： Akio Shima
IPC分类号： H01L21/336
CPC分类号： H01L21/8249 , H01L21/823814
摘要： A manufacturing technology of a MOSFET having a shallow junction and a source and drain of a low resistance is provided. After having ion-implanted an As on the surface of a p type well forming a gate electrode, a surface protection layer and an energy absorber layer are deposited on a substrate. When the surface of the substrate is irradiated by a YAG laser beam of the wavelength of 1064 nm for one nano second to 999 nano seconds, a heat absorbed by the energy absorber layer is transmitted to the substrate in an ultra short time, and heats its surface to a melting temperature, and therefore, the impurity is activated, and an extension region of a low resistance is formed in an extremely shallow region of about 20 nm in depth from the surface of the p type well.
摘要翻译：提供具有浅结的MOSFET和低电阻的源极和漏极的制造技术。在形成栅电极的p型阱的表面上离子注入As之后，在基板上沉积表面保护层和能量吸收层。当衬底的表面被波长为1064nm的YAG激光束照射一纳秒至999纳秒时，能量吸收层吸收的热量在极短的时间内被传送到衬底上，并将其加热表面到熔融温度，因此杂质被激活，并且从p型阱的表面开始深度约20nm的极浅的区域形成低电阻的延伸区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式