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31. 发明授权

US08687743B2 Methods and apparatus for detecting and decoding adaptive equalization training frames 有权
标题翻译：用于检测和解码自适应均衡训练帧的方法和装置
公开(公告)号：US08687743B2
公开(公告)日：2014-04-01
申请号：US13767307
申请日：2013-02-14
申请人： Agere Systems LLC
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/06
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame marker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用帧标记的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

32. 发明申请

US20130251140A1 Continuous Power Transfer Scheme for Two-Wire Serial Wire 审中-公开
标题翻译：双线串行线连续功率传输方案
公开(公告)号：US20130251140A1
公开(公告)日：2013-09-26
申请号：US13891643
申请日：2013-05-10
申请人： Agere Systems LLC
发明人： Johannes G. Ransijn , Boris A. Bark , James D. Yoder , Peter Kiss
IPC分类号： H04M3/00
CPC分类号： H04M3/005 , H04M19/001
摘要： The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.
摘要翻译：本发明提供了一种在DAA中的系统侧和线路侧电路之间的单个数字通信链路，能够承载数据信号并将大量电力传送到线路侧电路。本发明包括系统侧接口电路，线路侧接口电路和包括变压器的隔离屏障。每个接口电路能够连接到上游通信电路（线路侧或系统侧），从而可以接收要跨越隔离屏障传输到另一个接口电路的数据信号，并且其可以传递数据跨隔离屏障的信号与另一个接口电路接收。线路侧接口电路还可以包括整流器和存储设备。

33. 发明申请

US20130156086A1 METHODS AND APPARATUS FOR DETECTING AND DECODING ADAPTIVE EQUALIZATION TRAINING FRAMES 有权
标题翻译：用于检测和解码自适应均衡培训框架的方法和装置
公开(公告)号：US20130156086A1
公开(公告)日：2013-06-20
申请号：US13767307
申请日：2013-02-14
申请人： Agere Systems LLC
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame marker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用帧标记的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

34. 发明申请

US20130120867A1 Methods and Apparatus for Map Detection with Reduced Complexity 有权
标题翻译：降低复杂度的地图检测方法与装置
公开(公告)号：US20130120867A1
公开(公告)日：2013-05-16
申请号：US13736661
申请日：2013-01-08
申请人： Agere Systems LLC
发明人： Fitzpatrick Kelly K. , Erich F. Haratsch
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , H03M13/3905 , H03M13/395 , H03M13/6343 , H03M13/6502 , H04L1/0055 , H04L1/0066
摘要： Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft-output detector is provided for processing a received signal, comprising: a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states. A method is provided for processing a received signal using a soft-output detector, comprising: calculating forward state metrics using a forward detector; calculating backward state metrics using a backward detector; and calculating a current branch metric using a current branch detector, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states.
摘要翻译：提供了高速，低功耗，高性能通道检测的方法和装置。提供了一种用于处理接收信号的软输出检测器，包括：用于计算正向状态度量的正向检测器; 用于计算后向状态度量的反向检测器; 以及用于计算当前分支量度的当前分支检测器，其中所述正向检测器，所述后向检测器和所述当前支路检测器中的至少两个采用具有不同数量的状态的格状结构。提供一种用于使用软输出检测器处理接收信号的方法，包括：使用前向检测器来计算前向状态度量; 使用反向检测器计算后向状态度量; 以及使用当前分支检测器计算当前分支度量，其中所述正向检测器，所述后向检测器和所述当前支路检测器中的至少两个采用具有不同数量状态的格状结构。

35. 发明申请

US20130056868A1 ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER 审中-公开
标题翻译：用于替代互连层的BOND PAD路由器
公开(公告)号：US20130056868A1
公开(公告)日：2013-03-07
申请号：US13656092
申请日：2012-10-19
申请人： Agere Systems LLC
发明人： Vance D. Archer, III , Michael C. Ayukawa , Mark A. Bachman , Daniel P. Chesire , Seung H. Kang , Taeho Kook , Sailesh Merchant , Kurt G. Steiner
IPC分类号： H01L23/48 , H01L23/52 , H01L21/60
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05556 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13007 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2224/05552 , H01L2924/013
摘要： The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.
摘要翻译：本发明提供一种焊料凸块结构。在一个方面，焊料凸块结构用于诸如集成电路的半导体器件中。半导体器件包括位于半导体衬底之上的有源器件，包括形成在有源器件上的铜的互连层以及位于互连层上的最外层金属化层。最外面的金属化层包括铝，并且包括至少一个接合焊盘和至少一个互连转子，每一个电连接到互连层。凹凸金属化层（UBM）位于接合焊盘上方，焊料凸块位于UBM上方。

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