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31. 发明授权

US06969685B1 Etching a dielectric layer in an integrated circuit structure having a metal hard mask layer 有权
标题翻译：在具有金属硬掩模层的集成电路结构中蚀刻介电层
公开(公告)号：US06969685B1
公开(公告)日：2005-11-29
申请号：US10246926
申请日：2002-09-18
申请人： SiYi Li , S. M. Reza Sadjadi , Sean S. Kang
发明人： SiYi Li , S. M. Reza Sadjadi , Sean S. Kang
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/32136
摘要： The invention relates to the etching of a dielectric layer in an integrated circuit (IC) structure having a patterned metal hard mask layer. The method comprises feeding a gas mixture that includes a carbon monoxide (CO) and at least one fluorocarbon gas mixture into a reactor. The gas mixture has no oxygen (O2) gas. The gas mixture is then converted into a plasma. The plasma selectively etches the dielectric layer. Typically, the dielectric layer comprises silicon.
摘要翻译：本发明涉及具有图案化金属硬掩模层的集成电路（IC）结构中的介电层的蚀刻。该方法包括将包含一氧化碳（CO）和至少一种碳氟化合物气体混合物的气体混合物进料到反应器中。气体混合物没有氧（O 2/2）气体。然后将气体混合物转化成等离子体。等离子体选择性地蚀刻介电层。通常，电介质层包括硅。

32. 发明授权

US06908846B2 Method and apparatus for detecting endpoint during plasma etching of thin films 有权
标题翻译：用于在薄膜等离子体蚀刻期间检测端点的方法和装置
公开(公告)号：US06908846B2
公开(公告)日：2005-06-21
申请号：US10401114
申请日：2003-03-27
申请人： Brian K. McMillin , Eric Hudson , Jeffrey Marks
发明人： Brian K. McMillin , Eric Hudson , Jeffrey Marks
IPC分类号： H01L21/311 , H01L21/66 , H01L21/768 , H01L21/4763 , H01L21/302 , H01L23/48
CPC分类号： H01L21/76829 , H01J37/32963 , H01L21/31116 , H01L21/31138 , H01L21/76801 , H01L21/76807 , H01L22/26
摘要： A method for controlling a plasma etch process while etching a layer stack having a first layer disposed above an end-point generating layer is disclosed. The method includes etching through the first layer and at least partially through the end-point generating layer while monitoring an absorption rate of a light beam traversing an interior portion of the plasma processing chamber, wherein the end-point generating layer is selected from a material that produces a detectable change in the absorption rate when etched. The end-point generating layer is characterized by at least one of a first characteristic and a second characteristic. The first characteristic is an insufficient thickness to function as an etch stop layer, and the second characteristic is an insufficient selectivity to etchants employed to etch through the first layer to function as the etch stop layer. The method additionally includes generating an end-point signal upon detecting the detectable change.
摘要翻译：公开了一种用于在蚀刻具有设置在端点产生层上方的第一层的层堆叠的同时控制等离子体蚀刻工艺的方法。该方法包括：在监测穿过等离子体处理室的内部部分的光束的吸收率的同时，蚀刻穿过第一层并且至少部分地穿过端点产生层，其中端点产生层选自材料其在蚀刻时产生可检测的吸收速率变化。端点产生层的特征在于第一特征和第二特性中的至少一个。第一特征是不足以用作蚀刻停止层的厚度，并且第二特性对于用于蚀刻通过第一层以用作蚀刻停止层的蚀刻剂的选择性不足。该方法还包括在检测到可检测变化时产生端点信号。

33. 发明授权

US06896765B2 Method and apparatus for the compensation of edge ring wear in a plasma processing chamber 有权
标题翻译：用于补偿等离子体处理室中边缘磨损的方法和装置
公开(公告)号：US06896765B2
公开(公告)日：2005-05-24
申请号：US10247812
申请日：2002-09-18
申请人： Robert J. Steger
发明人： Robert J. Steger
IPC分类号： H05H1/46 , C23C16/50 , H01J37/32 , H01L21/3065 , H01L21/306
CPC分类号： H01J37/32623 , H01J37/32642
摘要： A method for processing a plurality of substrates in a plasma processing chamber of a plasma processing system, each of the substrate being disposed on a chuck and surrounded by an edge ring during the processing. The method includes processing a first substrate of the plurality of substrates in accordance to a given process recipe in the plasma processing chamber. The method further includes adjusting, thereafter, a capacitance value of a capacitance along a capacitive path between a plasma sheath in the plasma processing chamber and the chuck through the edge ring by a given value. The method additionally includes processing a second substrate of the plurality of substrates in accordance to the given process recipe in the plasma processing chamber after the adjusting, wherein the adjusting is performed without requiring a change in the edge ring.
摘要翻译：一种用于在等离子体处理系统的等离子体处理室中处理多个基板的方法，每个基板设置在卡盘上并且在处理期间被边缘环包围。该方法包括根据等离子体处理室中的给定工艺配方来处理多个基板中的第一基板。该方法还包括此后，通过等离子体处理室中的等离子体护套之间的电容路径和通过边缘环的卡盘之间的电容的电容值调整给定值。该方法另外包括在调整之后根据等离子体处理室中的给定工艺配方来处理多个基板中的第二基板，其中执行调整而不需要边缘环的改变。

34. 发明授权

US06889627B1 Symmetrical semiconductor reactor 有权
标题翻译：对称半导体反应堆
公开(公告)号：US06889627B1
公开(公告)日：2005-05-10
申请号：US10189111
申请日：2002-07-03
申请人： Fangli Hao
发明人： Fangli Hao
IPC分类号： H01L21/00 , C23C16/00 , H05H1/00
CPC分类号： H01L21/67126 , H01J37/32458
摘要： A symmetrical semiconductor reactor for semiconductor processing, comprising a liner, a process chamber, a valve chamber, a slot valve plate, a liner aperture plate, a rod, and an actuator. The liner has a liner aperture adapted to provide passage for a wafer and to receive the liner aperture plate. The process chamber is coupled to the liner and the valve chamber. The actuator is coupled to the slot valve plate and moves the slot valve plate from the “closed” to the “open” position and vice versa. Since the slot valve plate is coupled to the liner aperture plate by the rod, the actuator is capable of moving the slot valve plate and the liner aperture plate at the same time. However, the precise movements of the liner aperture plate are dependent on the particular rod embodiment.
摘要翻译：一种用于半导体加工的对称半导体反应器，包括衬套，处理室，阀室，槽阀板，衬里孔板，杆和致动器。衬里具有适于为晶片提供通道并接收衬垫孔板的衬里孔。处理室联接到衬套和阀室。致动器联接到槽阀板并将槽阀板从“关闭”位置移动到“打开”位置，反之亦然。由于槽阀板通过杆联接到衬套孔板，致动器能够同时移动槽阀板和衬套孔板。然而，衬套孔板的精确运动取决于具体的棒实施例。

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