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31. 发明授权

US08409978B2 Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe 有权
标题翻译：在引线框架上的迹线互连结构上形成垂直偏移键的半导体器件和方法
公开(公告)号：US08409978B2
公开(公告)日：2013-04-02
申请号：US12822504
申请日：2010-06-24
申请人： Reza A. Pagaila , KiYoun Jang , HunTeak Lee
发明人： Reza A. Pagaila , KiYoun Jang , HunTeak Lee
IPC分类号： H01L21/44
CPC分类号： H01L23/4952 , H01L23/3107 , H01L23/49513 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05001 , H01L2224/05082 , H01L2224/05111 , H01L2224/05155 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/16225 , H01L2224/2919 , H01L2224/32057 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/48249 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10161 , H01L2924/10162 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/0665 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.
摘要翻译：半导体器件具有垂直偏移的BOT互连结构。垂直偏移通过引线框架实现，引线框架具有围绕模板的多个引线。在引线指上形成第一导电层。在引线指上形成第二导电层。每个第二导电层定位成与第一导电层相邻，并且每个第一导电层定位成与第二导电层相邻。第二导电层的高度大于第一导电层的高度。第一和第二导电层可以具有并排布置或交错布置。在第一和第二导电层上形成凸起。接合线电连接到凸块。半导体管芯安装在引线框架的管芯上并电连接到接合线和BOT互连结构。

32. 发明授权

US08399990B2 Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD) 有权
标题翻译：在集成无源器件（IPD）中形成电容器和互连顶电极的方法
公开(公告)号：US08399990B2
公开(公告)日：2013-03-19
申请号：US13355354
申请日：2012-01-20
申请人： Yaojian Lin , Robert C. Frye
发明人： Yaojian Lin , Robert C. Frye
IPC分类号： H01L23/48
CPC分类号： H01L28/40 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2924/01079 , H01L2924/14 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105
摘要： A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
摘要翻译：一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。在基板和第一导电层上形成高电阻率层。介电层沉积在衬底，第一导电层和高电阻率层上。介电层，高电阻率层和第一导电层的一部分形成电容器叠层。在电介质层上形成第一钝化层。在电容器堆叠和第一钝化层的一部分上形成第二导电层。在电介质层中蚀刻第一开口以暴露高电阻率层的表面。在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

33. 发明授权

US08384227B2 Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die 有权
公开(公告)号：US08384227B2
公开(公告)日：2013-02-26
申请号：US12947442
申请日：2010-11-16
申请人： NamJu Cho , HeeJo Chi , HanGil Shin
发明人： NamJu Cho , HeeJo Chi , HanGil Shin
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/12 , H01L23/13 , H01L23/28 , H01L23/295 , H01L23/3107 , H01L23/3128 , H01L23/498 , H01L23/49811 , H01L23/49816 , H01L23/49833 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L2221/68327 , H01L2221/68381 , H01L2221/68386 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/06135 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/21 , H01L2224/2105 , H01L2224/215 , H01L2224/22 , H01L2224/221 , H01L2224/29144 , H01L2224/2919 , H01L2224/32013 , H01L2224/32059 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48101 , H01L2224/48105 , H01L2224/48145 , H01L2224/48157 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49 , H01L2224/73215 , H01L2224/73227 , H01L2224/73265 , H01L2224/73267 , H01L2224/85005 , H01L2224/85447 , H01L2224/92163 , H01L2224/92164 , H01L2224/95001 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06568 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/146 , H01L2924/15311 , H01L2924/171 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/18165 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H05K3/0052 , H01L2924/01014 , H01L2924/0665 , H01L2924/0105 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/81805 , H01L2224/85
摘要： A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

34. 发明授权

US08354304B2 Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant 有权
公开(公告)号：US08354304B2
公开(公告)日：2013-01-15
申请号：US12329430
申请日：2008-12-05
申请人： Seng Guan Chow , Il Kwon Shim , Heap Hoe Kuan , Rui Huang
发明人： Seng Guan Chow , Il Kwon Shim , Heap Hoe Kuan , Rui Huang
IPC分类号： H01L21/00
CPC分类号： H01L23/49811 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/48 , H01L24/97 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/48091 , H01L2224/73265 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts.

35. 发明授权

US08317358B2 Method and apparatus for providing an omni-directional lamp having a light emitting diode light engine 有权
标题翻译：用于提供具有发光二极管光引擎的全方向灯的方法和装置
公开(公告)号：US08317358B2
公开(公告)日：2012-11-27
申请号：US12236993
申请日：2008-09-24
申请人： Der Jeou Chou
发明人： Der Jeou Chou
IPC分类号： F21V7/20 , F21V29/00
CPC分类号： F21V29/51 , F21K9/232 , F21V29/006 , F21V29/767 , F21V29/773 , F21V29/777 , F21V29/80 , F21Y2107/00 , F21Y2115/10
摘要： An LED lamp includes a light engine. The light engine includes a substrate including a transparent or translucent thermally conductive material, a plurality of LED semiconductor devices mounted to the substrate, a plurality of conductive traces formed over the substrate to electrically interconnect each of the plurality of LED semiconductor devices, and conductive leads connected to the substrate for supplying electrical energy to the plurality of LED semiconductor devices. The substrate of the light engine may include an aluminum nitride (AlN), or diamond film material. A thermally conductive rod is connected to the light engine. A heatsink is formed by an extrusion or die casting process. The heatsink includes a fin structure for dissipating heat energy into the environment. The thermally conductive rod and the heatsink are thermally connected. An optional optical envelope is mounted to the heatsink. The optional optical envelope is disposed over the light engine.
摘要翻译： LED灯包括光引擎。所述光引擎包括：基板，其包括透明或半透明的导热材料，安装到所述基板的多个LED半导体器件，形成在所述基板上方的多个导电迹线，以电连接所述多个LED半导体器件中的每一个;以及导电引线连接到用于向多个LED半导体器件提供电能的基板。光引擎的基板可以包括氮化铝（AlN）或金刚石膜材料。导热棒连接到光引擎。通过挤压或压铸工艺形成散热片。散热器包括用于将热能耗散到环境中的翅片结构。导热棒和散热片被热连接。可选的光学信封安装在散热器上。可选的光学信封设置在光引擎上。

36. 发明授权

US08309452B2 Method of forming an inductor on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成电感器的方法
公开(公告)号：US08309452B2
公开(公告)日：2012-11-13
申请号：US12826365
申请日：2010-06-29
申请人： Yaojian Lin , Haijing Cao , Qing Zhang
发明人： Yaojian Lin , Haijing Cao , Qing Zhang
IPC分类号： H01L21/44 , H01L21/60
CPC分类号： H01L23/5227 , H01L23/645 , H01L24/03 , H01L24/05 , H01L24/48 , H01L28/10 , H01L2224/02166 , H01L2224/04042 , H01L2224/056 , H01L2224/451 , H01L2224/48463 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/00 , H01L2224/45099
摘要： A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.
摘要翻译：半导体器件具有在其表面上形成有电感器的基板。第一和第二接触垫形成在基板上。在衬底和第一和第二接触焊盘之上形成钝化层。在钝化层上形成保护层。保护层在第一接触垫上移除，但不从第二接触垫移除。导电层形成在第一接触焊盘上。导电层被卷绕在基板的表面上以产生电感性质。导电层的形成涉及使用湿蚀刻剂。第二接触垫被保护层从湿蚀刻剂保护。在第一接触垫上形成导电层之后，从第二接触焊盘去除保护层。在第二接触垫上形成外部连接。

37. 发明授权

US08304904B2 Semiconductor device with solder bump formed on high topography plated Cu pads 有权
标题翻译：具有焊料凸块的半导体器件形成在高地形电镀铜焊盘上
公开(公告)号：US08304904B2
公开(公告)日：2012-11-06
申请号：US12700114
申请日：2010-02-04
申请人： Yaojian Lin , Qing Zhang , Haijing Cao
发明人： Yaojian Lin , Qing Zhang , Haijing Cao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L2224/0231 , H01L2224/03912 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05647 , H01L2224/11009 , H01L2224/11019 , H01L2224/13022 , H01L2224/131 , H01L2224/13109 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2224/13099 , H01L2224/05552
摘要： A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.
摘要翻译：半导体器件具有形成在衬底上的第一导电层。第一绝缘层形成在衬底和第一导电层上。在第一导电层和第一绝缘层上形成第二导电层。在第一绝缘层和第二导电层上形成第二绝缘层。第二绝缘层在第二绝缘材料的表面和第二导电层的表面之间具有侧壁。在第二绝缘层和第二导电层的表面上形成保护层。保护层遵循第二绝缘层和第二导电层的表面和侧壁的轮廓。在第二导电层的表面上形成凸块，并且与第二绝缘层相邻的部分形成保护层。保护层保护第二绝缘层。

38. 发明授权

US08288202B2 Method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die 有权
标题翻译：形成部分蚀刻的导电层的方法，该导电层凹入衬底内用于接合到半导体管芯
公开(公告)号：US08288202B2
公开(公告)日：2012-10-16
申请号：US12951399
申请日：2010-11-22
申请人： KyuWon Lee , HyunSu Shin , Hun Jeong , JinGwan Kim , SunYoung Chun
发明人： KyuWon Lee , HyunSu Shin , Hun Jeong , JinGwan Kim , SunYoung Chun
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/52 , H01L21/563 , H01L23/3128 , H01L23/48 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/94 , H01L25/105 , H01L25/50 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/16225 , H01L2224/1718 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/83102 , H01L2224/92125 , H01L2224/94 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00014 , H01L2224/81805
摘要： A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
摘要翻译：半导体器件具有具有管芯附着区域的衬底。导电层形成在衬底的表面上并在表面下方延伸。在芯片附着区域外部的基板的表面上形成绝缘层。导电层的一部分在管芯附着区域内去除以暴露衬底的侧壁。导电层的剩余部分在芯片附着区域内凹陷在基板的表面下方。半导体管芯在其有效表面上形成凸块。半导体管芯通过将凸起焊接到凹陷在基板的第一表面下方的第一导电层的剩余部分而安装到基板。在与导电层的剩余部分接合期间，衬底的侧壁保持凸块。密封剂沉积在半导体管芯和衬底之间。

39. 发明授权

US08283250B2 Semiconductor device and method of forming a conductive via-in-via structure 有权
标题翻译：半导体器件和形成导电通孔在通孔结构的方法
公开(公告)号：US08283250B2
公开(公告)日：2012-10-09
申请号：US12332318
申请日：2008-12-10
申请人： Lionel Chien Hui Tay , Jianmin Fang , Zigmund R. Camacho
发明人： Lionel Chien Hui Tay , Jianmin Fang , Zigmund R. Camacho
IPC分类号： H01L21/20
CPC分类号： H01L23/481 , H01L21/76898 , H01L2224/04042 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/16225 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area.
摘要翻译：半导体器件由包含由周边区域分离的半导体管芯的半导体晶片制成。在周边区域或通过器件的有源区域形成导电通孔结构，以提供额外的拉伸强度。导电通孔结构包括由绝缘材料隔开的内部导电通孔和外部导电通孔。中间导电通孔可以形成在内导电通孔和外导电通孔之间。内部导电通孔具有与半导体器件的第一表面相邻的第一横截面区域和与半导体器件的第二表面相邻的第二横截面区域。外导电通孔具有与半导体器件的第一表面相邻的第一横截面区域和与半导体器件的第二表面相邻的第二横截面区域。第一截面积与第二横截面积不同。

40. 发明授权

US08263435B2 Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias 有权
标题翻译：半导体器件和堆叠半导体裸片在模具激光器封装中通过凸块和导电通孔互连的方法
公开(公告)号：US08263435B2
公开(公告)日：2012-09-11
申请号：US12914895
申请日：2010-10-28
申请人： DaeSik Choi , WonJun Ko , JaEun Yun
发明人： DaeSik Choi , WonJun Ko , JaEun Yun
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/565 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2224/02371 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06182 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/221 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73209 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81005 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06568 , H01L2225/06589 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2225/1088 , H01L2225/1094 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/14364 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/00 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.
摘要翻译：半导体晶片包含多个第一半导体管芯。半导体晶片安装在载体上。通过半导体晶片形成通道以分离第一半导体管芯。第二半导体管芯安装到第一半导体管芯。密封剂沉积在载体和第一半导体管芯上并进入沟道，同时第二半导体管芯的侧部和表面部分保持暴露于密封剂。通过通道中的密封剂形成第一导电通孔。第二导电通孔在第一半导体管芯的接触焊盘上穿过密封剂形成。在第一和第二导电通孔之间的密封剂之上形成导电层。在导电层和密封剂之上形成绝缘层。载体被移除。互连结构形成在第一导电通孔上。

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