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31. 发明授权

US09053217B2 Ratio-adjustable sync mark detection system 有权
标题翻译：比率可调同步标记检测系统
公开(公告)号：US09053217B2
公开(公告)日：2015-06-09
申请号：US13777937
申请日：2013-02-26
申请人： LSI Corporation
发明人： Rui Cao , Yu Kou , Shaohua Yang
IPC分类号： G11B5/09 , G06F11/34 , G11B27/00 , H04L1/00
CPC分类号： G06F11/34 , G11B5/59616 , G11B20/10 , G11B20/1403 , G11B27/00 , H04L1/00
摘要： Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system.
摘要翻译：用于数据处理的系统，方法，设备，电路，更具体地涉及用比率可调检测系统检测同步标记的系统和方法。

32. 发明申请

US20150154138A1 WIDE PORT EMULATION AT SERIAL ATTACHED SCSI EXPANDERS 有权
标题翻译：串行连接SCSI扩展器的宽端口仿真
公开(公告)号：US20150154138A1
公开(公告)日：2015-06-04
申请号：US14096204
申请日：2013-12-04
申请人： LSI CORPORATION
发明人： Shankar More , Mandar Joshi , Vidyadhar Pinglikar
IPC分类号： G06F13/40
CPC分类号： G06F13/4059 , G06F13/385 , G06F13/404
摘要： Methods and structure for emulating wide ports at an expander are provided. An exemplary system includes a Serial Attached Small Computer System Interface (SAS) expander. The expander includes a plurality of physical links, and a controller. The controller is able to identify a physical link coupled with a device, to generate a plurality of virtual physical links that are configured as a virtual wide port coupled with the device, and to present the virtual wide port at the expander in place of the physical link.
摘要翻译：提供了在扩展器上模拟宽端口的方法和结构。示例性系统包括串行连接小型计算机系统接口（SAS）扩展器。扩展器包括多个物理链路和控制器。控制器能够识别与设备耦合的物理链路，以产生被配置为与设备耦合的虚拟宽端口的多个虚拟物理链路，并且在扩展器处呈现虚拟宽端口以代替物理链接。

33. 发明授权

US09048873B2 Systems and methods for multi-stage encoding of concatenated low density parity check codes 有权
标题翻译：连接低密度奇偶校验码的多级编码的系统和方法
公开(公告)号：US09048873B2
公开(公告)日：2015-06-02
申请号：US13912079
申请日：2013-06-06
申请人： LSI Corporation
发明人： Zongwang Li , Yu Kou , Chung-Li Wang , Shaohua Yang , Shu Li
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/1171 , H03M13/611 , H03M13/616
摘要： A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.
摘要翻译：数据编码系统包括数据编码器电路，其可操作以用低密度奇偶校验码矩阵的分量矩阵对多个数据扇区中的每一个进行编码，并产生输出码字。数据编码器电路包括可用于计算和组合用于数据扇区的综合征的校正子计算电路。

34. 发明申请

US20150143164A1 I/O REQUEST MIRRORING IN A CLUSTERED STORAGE SYSTEM 有权
标题翻译：集成存储系统中的I / O请求镜像
公开(公告)号：US20150143164A1
公开(公告)日：2015-05-21
申请号：US14085465
申请日：2013-11-20
申请人： LSI Corporation
发明人： Sridhar Rao Veerla , Naveen Krishnamurthy
IPC分类号： G06F11/16 , G06F11/26
CPC分类号： G06F11/167 , G06F11/0727 , G06F11/1092 , G06F11/1612 , G06F11/2023 , G06F11/2053 , G06F11/2069 , G06F11/2071
摘要： Clustered storage systems and methods are presented herein. One clustered storage system includes a logical volume comprising first and second pluralities of storage devices. The first plurality of storage devices is different from the second plurality of storage devices and includes at least the same data as the second plurality of devices. The storage system also includes a first storage node operable to process first I/O requests to the first plurality of storage devices and a second storage node communicatively coupled to the first storage node and operable to process second I/O requests to the second plurality of storage devices. An I/O request of the first I/O requests initiates a redirection condition that the first storage node detects. Then, based on the redirection condition, the first storage node directs the second storage node to process data of the I/O request.
摘要翻译：本文介绍了集群存储系统和方法。一个集群存储系统包括包括第一和第二多个存储设备的逻辑卷。第一多个存储装置与第二多个存储装置不同，并且至少包括与第二多个装置相同的数据。存储系统还包括第一存储节点，其可操作以处理对第一多个存储设备的第一I / O请求;以及第二存储节点，其通信地耦合到第一存储节点，并且可操作以将第二I / O请求处理到第二多个存储设备。第一个I / O请求的I / O请求启动第一个存储节点检测到的重定向条件。然后，基于重定向条件，第一存储节点指示第二存储节点处理I / O请求的数据。

35. 发明申请

US20150135032A1 Detection/Erasure of Random Write Errors Using Converged Hard Decisions 有权
标题翻译：使用融合硬判决检测/擦除随机写入错误
公开(公告)号：US20150135032A1
公开(公告)日：2015-05-14
申请号：US14150810
申请日：2014-01-09
申请人： LSI CORPORATION
发明人： Abdel-Hakim S. Alhussien , Erich F. Haratsch , Yunxiang Wu
IPC分类号： G06F11/10 , G11C29/50
CPC分类号： G06F11/1072 , G06F11/1012 , G11C11/56 , G11C29/42 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004 , H03M13/1105 , H03M13/1142 , H03M13/3723 , H03M13/373 , H03M13/3769 , H03M13/451
摘要： A low-density parity-check decoder in a system with multi-level cells identifies zones of reliability where write errors or stuck cells are identifiable. The system uses assumedly successfully decoded pages associated with bits in a cell to identify candidate write errors or stuck cells and erases a corresponding log-likelihood ratio even where such log-likelihood ratio is saturated, thereby breaking a potential trapping set without post-processing.
摘要翻译：具有多级单元的系统中的低密度奇偶校验解码器识别写入错误或被卡住的单元是可识别的可靠性区域。该系统使用与单元中的位相关联的假设成功解码的页面来识别候选写入错误或卡住的单元并且擦除相应的对数似然比，即使这样的对数似然比饱和，从而破坏潜在的陷阱集而不进行后处理。

36. 发明授权

US09026891B2 Method for format savings in coherently written fragmented sectors 有权
标题翻译：一致写入分散行业节省格式的方法
公开(公告)号：US09026891B2
公开(公告)日：2015-05-05
申请号：US13831246
申请日：2013-03-14
申请人： LSI Corporation
发明人： Scott M. Dziak , Jeffrey P. Grundvig , Jason D. Byrne
IPC分类号： G11C29/00 , G11B27/30 , G11B20/12 , G06F11/10 , G11B20/10
CPC分类号： G11B27/3027 , G06F11/1076 , G11B20/1217 , G11B2020/10916 , G11B2020/1232
摘要： A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.
摘要翻译：一种用于对具有相干写入的片段的至少一个数据扇区的至少一个片段执行缩短的获取周期的方法和系统，所述相干写入的片段在存储介质的单次旋转期间被写入。该方法包括对至少一个数据扇区的特定数据扇区的第一片段执行完整采集周期。该方法还包括重新使用第一片段的获取信息的至少一部分来对至少一个随后的相干写入片段执行缩短的获取周期。该方法还包括重新利用第一片段的获取信息的至少一部分来对至少一个随后的相干写入片段执行缩短的获取周期。另外，该方法包括对所述至少一个随后的相干写入片段执行缩短的获取周期。

37. 发明授权

US09026706B2 Method and system for detecting multiple expanders in an SAS topology having the same address 有权
标题翻译：用于检测具有相同地址的SAS拓扑中的多个扩展器的方法和系统
公开(公告)号：US09026706B2
公开(公告)日：2015-05-05
申请号：US13715103
申请日：2012-12-14
申请人： LSI Corporation
发明人： Raghavendra Channagiri Nagendra , Giridhar Danayakanakeri , Prashant Prakash Yendigiri
IPC分类号： G06F13/40
CPC分类号： G06F13/4063
摘要： Methods, systems, and processor-readable media are disclosed for detecting multiple expanders in a SAS topology having the same address. A root expander can be connected to a plurality of expanders, wherein one or more expanders among the plurality of expanders possesses a same SAS address as the root expander. The same SAS address can be identified and stored in a route table against a physical layer identifier through which the expander(s) communicate with the root expander in order to assist in identifying duplicate expanders in the SAS topology.
摘要翻译：公开了用于检测具有相同地址的SAS拓扑中的多个扩展器的方法，系统和处理器可读介质。根扩展器可以连接到多个扩展器，其中多个扩展器中的一个或多个扩展器具有与根扩展器相同的SAS地址。可以根据物理层标识符识别相同的SAS地址并将其存储在路由表中，扩展器通过该物理层标识符与根扩展器通信，以帮助识别SAS拓扑中的重复扩展器。

38. 发明授权

US09025655B1 Transmitter training using receiver equalizer coefficients 有权
标题翻译：使用接收机均衡器系数的发射机训练
公开(公告)号：US09025655B1
公开(公告)日：2015-05-05
申请号：US14072895
申请日：2013-11-06
申请人： LSI Corporation
发明人： Rajesh Ramadoss , Mohammad S. Mobin , Thomas F. Gibbons, Jr.
IPC分类号： H03H7/30 , H04L25/03
CPC分类号： H04L25/03885 , H04L25/03057 , H04L25/03343
摘要： A method of adjusting a post-cursor tap weight in a transmitter FIR filter in a high-speed digital data transmission system. A receiver, over a forward channel, receives a signal from the transmitter and equalizes the received signal using an adaptive analog equalizer coupled to the forward channel and a decision feedback equalizer (DFE) coupled to the analog equalizer. A gain coefficient used to adjust the peaking by the analog equalizer is adapted using an error signal generated by the DFE. The post-cursor tap weight of the transmitter filter is adjusted up or down based on a comparison of the gain coefficient to a set. of limits. The post-cursor tap weight is transmitted to the transmitter over a reverse channel and then equalizers in the receiver readapt. Alternatively, eye opening data and a DFE tap coefficient are used to determine whether the post-cursor tap weight is adjusted up or down.
摘要翻译：一种在高速数字数据传输系统中调整发射机FIR滤波器中的后光标抽头权重的方法。接收机通过前向信道接收来自发射机的信号，并使用耦合到前向信道的自适应模拟均衡器和耦合到模拟均衡器的判决反馈均衡器（DFE）来均衡接收信号。用于通过模拟均衡器调节峰值的增益系数使用DFE产生的误差信号进行调整。基于增益系数与一组的比较，发送器滤波器的后置光标重量被上下调整。的限制。后置光标抽头权重通过反向通道发送到发送器，然后在接收器中对其进行均衡。或者，使用眼睛打开数据和DFE抽头系数来确定是否向上或向下调整后光标抽头重量。

39. 发明授权

US09021325B2 Classifying bit errors in transmitted run length limited data 有权
标题翻译：对发送的运行长度限制数据中的位错误进行分类
公开(公告)号：US09021325B2
公开(公告)日：2015-04-28
申请号：US13761427
申请日：2013-02-07
申请人： LSI Corporation
发明人： Coralyn S. Gauvin , Gabriel L. Romero
IPC分类号： G01R31/28 , G06F11/00 , G06F11/08 , G06F11/277 , G01R31/3193
CPC分类号： G01R31/3193 , G06F11/076 , G06F11/0763 , G06F11/08 , G06F11/277 , H04L1/241
摘要： A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
摘要翻译：测试模式使用游程长度限制行编码来编码以产生编码的数据块。编码的数据块通过信道发送。在发送数据中的最大长度运行之后的所接收的数据块中的多个比特与预期的多个比特进行比较。基于预期的多个比特和接收的数据块中的多个比特之间的不匹配来分类一种比特错误。

40. 发明授权

US09021199B2 Methods and structure for normalizing storage performance across a plurality of logical volumes 有权
标题翻译：在多个逻辑卷上归一化存储性能的方法和结构
公开(公告)号：US09021199B2
公开(公告)日：2015-04-28
申请号：US13586133
申请日：2012-08-15
申请人： Nilesh S. Govande , Jameer Babasaheb Mulani , Brad D. Besmer , Susan Gray
发明人： Nilesh S. Govande , Jameer Babasaheb Mulani , Brad D. Besmer , Susan Gray
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/061 , G06F3/0628 , G06F3/0631 , G06F3/067 , G06F3/0673 , G06F12/02
摘要： Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance zones exhibit different performance criteria for one or more of: reading data from the storage device and writing data to the storage device. The storage controller is further adapted to allocate storage from each of the plurality of performance zones for each of the plurality of logical volumes such that the performance criteria for accessing the storage device is distributed substantially uniformly across the plurality of logical volumes.
摘要翻译：公开了用于在多个逻辑卷上归一化存储性能的方法和结构。一个实施例是存储控制器。存储控制器适于与多个主机系统和存储设备耦合。存储控制器适于接收一个或多个请求以为多个软管系统创建逻辑卷，并且适于识别用于存储设备的存储区域的多个性能区域。性能区域对于以下中的一个或多个呈现不同的性能标准：从存储设备读取数据并将数据写入存储设备。存储控制器还适用于为多个逻辑卷中的每一个为多个性能区域中的每一个分配存储，使得用于访问存储设备的性能标准基本上均匀地分布在多个逻辑卷上。

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