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31. 发明授权

US09905995B2 Adjustable termination circuit for high speed laser driver 有权
公开(公告)号：US09905995B2
公开(公告)日：2018-02-27
申请号：US15252877
申请日：2016-08-31
申请人： Integrated Device Technology, Inc.
发明人： Samuel Aloysius Steidl , Emad Afifi
IPC分类号： H01S5/042 , H01S5/062
CPC分类号： H01S5/0427 , H01S5/06226
摘要： Disclosed is a circuit having a high speed laser driver circuit, a semiconductor laser electrically connected to the high speed laser driver circuit, and an adjustable termination circuit electrically connected between the high speed laser driver circuit and the semiconductor laser, where the adjustable termination circuit is configured to control an output impedance seen by the semiconductor laser as a function of an input current provided to the adjustable termination circuit.

32. 发明授权

US09905287B2 Asymmetrical emphasis in a memory data bus driver 有权
公开(公告)号：US09905287B2
公开(公告)日：2018-02-27
申请号：US15480616
申请日：2017-04-06
申请人： Integrated Device Technology, Inc.
发明人： Yanbo Wang , Praveen Rajan Singh , Yue Yu , Craig DeSimone
IPC分类号： G11C11/4093 , G06F13/40 , G11C11/4076 , H04L25/02
CPC分类号： G11C11/4093 , G06F13/4068 , G06F13/4072 , G11C5/04 , G11C7/1057 , G11C7/1084 , G11C11/4076 , H04L25/028 , H04L25/0286
摘要： An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

33. 发明申请

US20180005470A1 WIRELESS POWERED DIGITAL LOCK 审中-公开
公开(公告)号：US20180005470A1
公开(公告)日：2018-01-04
申请号：US15633231
申请日：2017-06-26
申请人： Integrated Device Technology, Inc.
发明人： Christopher STEPHENS , Jianbin HAO , Pietro POLIDORI , Giulio SPINELLI
IPC分类号： G07C9/00 , E05B47/00 , H04B5/00
CPC分类号： G07C9/00571 , E05B47/0001 , G07C9/00309 , G07C2009/00634 , G07C2009/00769 , G07C2209/64 , H04B5/0037
摘要： An electronic lock that interacts with a mobile device is presented. In accordance with some embodiments, an electronic lock includes a wireless power receiver configured to receiver power from a mobile device; a processor coupled to receive power from the wireless power receiver; a memory coupled to the processor and to receive power from the wireless power receiver; a communication unit coupled to the processor and to receive power from the wireless power receiver, the communication unit configured to communicate with the mobile device; and an actuator coupled to the processor and to receive power from the wireless power receiver. The processor executes instructions stored in a memory for authenticating the mobile device, and providing signals to the actuator according to instructions received from the mobile device once it is authenticated. The mobile device provides power to the electronic lock and instructs it to lock or unlock a locking mechanism.

34. 发明授权

US09860535B2 Method for time-dependent visual quality encoding for broadcast services 有权
公开(公告)号：US09860535B2
公开(公告)日：2018-01-02
申请号：US14717931
申请日：2015-05-20
申请人： Integrated Device Technology, Inc.
发明人： Lowell Leroy Winger
IPC分类号： H04N19/179 , H04N19/162 , H04N19/156 , H04N19/115
CPC分类号： H04N19/115 , H04N19/156 , H04N19/162 , H04N19/179
摘要： Apparatuses and methods for adjusting an encoding profile to change the visual quality of broadcast video based, at least in part, on a time of day. An example apparatus may include an encoder configured to receive a video input and provide an encoded bitstream based at least in part on an encoding profile, wherein the encoder is further configured to determine the encoding profile based on a time of day. An example method may include encoding images based on a first profile during a first time period, changing to a second profile based on a second time period, and encoding images based on the second profile during the second time period.

35. 发明授权

US09847869B1 Frequency synthesizer with microcode control 有权
公开(公告)号：US09847869B1
公开(公告)日：2017-12-19
申请号：US15210204
申请日：2016-07-14
申请人： Integrated Device Technology, Inc.
发明人： Chung-Yu Wu , Wei-Ching Chan , John Hsu , Cheng Wen Hsiao
IPC分类号： H03D3/24 , H04L7/033 , H04L12/70
CPC分类号： H03L7/104 , H03L7/183 , H04L2012/5681
摘要： A frequency synthesizer with microcode control that allows one or more programmable circuits of a frequency synthesizer system to be programmed using a plurality of microcode instructions. A method includes, setting a frequency synthesizer system to operate in a microcode mode, programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions and executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.

36. 发明授权

US09838016B1 Adaptive high-speed current-steering logic (HCSL) drivers 有权
公开(公告)号：US09838016B1
公开(公告)日：2017-12-05
申请号：US15050646
申请日：2016-02-23
申请人： Integrated Device Technology, Inc.
发明人： Pengfei Hu
IPC分类号： H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018514
摘要： A packaged integrated circuit device includes a first driver, which has a first pair of differential output terminals and a first common-mode sensing terminal, and a second driver, which has a second pair of differential output terminals and a second common-mode sensing terminal. The second driver can be a smaller scaled replica of the first driver. A comparator and a reference signal generator are provided. The comparator is configured to compare first and second common-mode voltage signals developed at the first and second common-mode sensing terminals, respectively, and the reference signal generator is configured to provide the first and second drivers with a reference voltage having a magnitude that varies in response to changes in a signal generated at an output terminal of the comparator. This variation in the magnitude of the reference voltage supports a built-in adaptive response to changes in source-side termination in HCSL driver/receiver circuits.

37. 发明授权

US09712041B2 Apparatuses and methods for over-current protection of DC-DC voltage converters 有权
公开(公告)号：US09712041B2
公开(公告)日：2017-07-18
申请号：US14109743
申请日：2013-12-17
申请人： Integrated Device Technology, Inc.
发明人： Rosario Pagano
IPC分类号： H02M1/32 , G01R19/04 , G01R19/00 , H02H7/12 , H02M3/158 , H02M1/00
CPC分类号： H02M1/32 , G01R19/0092 , G01R19/04 , H02H7/1213 , H02M3/158 , H02M2001/0009
摘要： A peak current protection circuit includes a current sensing circuit configured to sense an operating current of a DC-DC converter, and an over-current detector operably coupled with the current sensing circuit. The over-current detector is configured to generate an over-current detect signal at a peak current limit that is that is independent of a voltage level of an output signal of the DC-DC converter. A method for providing over-current protection for a DC-DC converter includes sensing an operating current of a DC-DC converter at a first input of a comparator, sensing a reference current at a second input of the comparator, comparing the first input with the second input, and generating an over-current detect signal in response to the comparison such that a peak current limit for the DC-DC converter is independent of a voltage level of an output signal of the DC-DC converter.

38. 发明申请

US20170166442A1 SYSTEM AND METHOD FOR PROVIDING HERMETICALLY SEALED PACKAGES WITH CONSISTENT VACUUM CAVITY 审中-公开
公开(公告)号：US20170166442A1
公开(公告)日：2017-06-15
申请号：US14967007
申请日：2015-12-11
申请人： INTEGRATED DEVICE TECHNOLOGY, INC.
发明人： Srikanth Kulkarni , Viresh P. Patel
IPC分类号： B81C1/00 , H01L21/52
CPC分类号： B81C1/00269 , B81C2203/019 , H01L21/50
摘要： A method of forming a plurality of sealed packages comprises providing a base including a base surface; providing a lid including a lid surface; positioning a plurality of spaced apart seal members along the base surface, the seal members being formed from a seal material including a fusible metal alloy; positioning the lid on the base with a plurality of spaced apart spacers positioned and extending between the base surface and the lid surface, the spacers maintaining the lid surface spaced apart from the seal members by a fluid gap, the spacers being made from a spacer material including a fusible metal alloy; creating a controlled environment around the base and the lid; and heating to melt the spacers and the seal material so that the seal members form a plurality of seal rings between the base surface and the lid surface.

39. 发明授权

US09628255B1 Methods and apparatus for transmitting data over a clock signal 有权
公开(公告)号：US09628255B1
公开(公告)日：2017-04-18
申请号：US14975226
申请日：2015-12-18
申请人： Integrated Device Technology, Inc.
发明人： Zaher Baidas , Bogdan Staicu , Menno Tjeerd Spijker
IPC分类号： H04L7/00
CPC分类号： H04L5/00 , H04L7/0008 , H04L25/49
摘要： A method of operating a clock circuit can include transmitting a clock signal from a transmitter of a first system to a receiver of a second system, where a first repeating edge of a clock cycle of the clock signal repeats at a predetermined constant frequency within the clock signal to synchronize operations of the second system, and varying, by the first system, a second edge within the clock cycle of the clock signal to transmit a data transmission within the clock signal.

40. 发明授权

US09583155B1 Single-ended signal slicer with a wide input voltage range 有权
标题翻译：具有宽输入电压范围的单端信号限幅器
公开(公告)号：US09583155B1
公开(公告)日：2017-02-28
申请号：US15093876
申请日：2016-04-08
申请人： Integrated Device Technology, Inc.
发明人： Yi Xie , Yuan Zhang
IPC分类号： G11C5/14 , G11C5/06 , G11C8/18 , G11C7/22 , G11C7/10
CPC分类号： G11C5/063 , G11C5/147 , G11C7/1084 , G11C7/22 , G11C8/18
摘要： An apparatus includes a first circuit, a second circuit, and a third circuit. The first circuit may be configured to (i) reduce a current value in a sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel to generate a version of the current value, and (ii) reduce a first reference voltage to generate a second reference voltage. The second circuit may be configured to slice the current value with respect to the first reference voltage to generate a first intermediate value. The third circuit may be configured to slice the version of the current value with respect to the second reference voltage to generate a second intermediate value. The first intermediate value and the second intermediate value generally define a sliced value of the current value.
摘要翻译：一种装置包括第一电路，第二电路和第三电路。第一电路可以被配置为（i）减少已经在耦合到存储器通道的数据总线的单端行上承载的输入值序列中的电流值，以生成当前值的版本，并且（ ii）减小第一参考电压以产生第二参考电压。第二电路可以被配置为相对于第一参考电压分割电流值以产生第一中间值。第三电路可以被配置为相对于第二参考电压分割当前值的版本以生成第二中间值。第一中间值和第二中间值通常定义当前值的切片值。

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