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31. 发明授权

US06941545B1 Profiling of computer programs executing in virtual memory systems 有权
标题翻译：在虚拟内存系统中执行的计算机程序的分析
公开(公告)号：US06941545B1
公开(公告)日：2005-09-06
申请号：US09322443
申请日：1999-05-28
申请人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
发明人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
IPC分类号： G06F9/455 , G06F9/44
CPC分类号： G06F9/45554 , G06F9/45541 , G06F9/45558 , G06F2009/45583
摘要： A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.
摘要翻译：一台电脑。指令流水线和存储器访问单元在计算机的存储器的逻辑地址空间中执行指令。地址转换电路将由程序生成的地址参考从程序的逻辑地址空间转换为计算机的物理地址空间。简档电路与指令流水线协作地互连，并且被配置为在没有编译器帮助执行分析的情况下检测在指令流水线中发生的可概要事件的发生，并且与存储器访问单元协作地互连以记录描述参考的物理存储器地址的简档信息程序的执行间隔。

32. 发明授权

US06934832B1 Exception mechanism for a computer 有权
公开(公告)号：US06934832B1
公开(公告)日：2005-08-23
申请号：US09667226
申请日：2000-09-21
申请人： Korbin S. Van Dyke , Paul Campbell , Shalesh Thusoo , T. R. Ramesh , Alan McNaughton
发明人： Korbin S. Van Dyke , Paul Campbell , Shalesh Thusoo , T. R. Ramesh , Alan McNaughton
IPC分类号： G06F11/00
CPC分类号： G06F9/30174 , G06F9/3851 , G06F9/3861
摘要： A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers. The processor registers of the computer are designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory, the processor registers and general purpose registers of the computer together providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory.

33. 发明授权

US06934389B2 Method and apparatus for providing bus-encrypted copy protection key to an unsecured bus 有权
标题翻译：将总线加密的复制保护密钥提供给不安全的总线的方法和装置
公开(公告)号：US06934389B2
公开(公告)日：2005-08-23
申请号：US09798538
申请日：2001-03-02
申请人： David A. Strasser , Edwin Pang , Gabriel Z. Varga
发明人： David A. Strasser , Edwin Pang , Gabriel Z. Varga
IPC分类号： H04L9/08 , H04L9/30 , H04N7/167 , H04N21/418 , H04N21/4367 , H04L9/00
CPC分类号： H04N21/4181 , H04L9/0841 , H04L9/0891 , H04L2209/605 , H04N7/1675 , H04N21/4367
摘要： A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus. The locally exchanged public keys are shorter in length than those used between the CPU and POD to produce the original CP key.
摘要翻译：由POD等发送源用于加密诸如音频和/或视频信息的内容的复制保护（CP）密钥由与第一处理器相关联的第一密钥生成器导出，并且由第一处理器本地加密使用本地生成的总线加密密钥，以产生通过本地不安全总线发送到诸如图形处理器的第二处理器的总线加密CP密钥。第二处理器使用解密引擎解密总线加密复制密钥以获得CP密钥。第二处理器接收加密的内容，并且在一个实施例中，也使用相同的解密引擎来解密加密的内容。第一和第二处理器在本机之间本地交换公共密钥本地导出用于在通过不安全总线发送之前对CP密钥进行加密的总线加密密钥，并且在通过总线发送之后解密加密的CP密钥。本地交换的公钥的长度要比在CPU和POD之间使用的公钥短，以产生原始的CP密钥。

34. 发明授权

US06907597B1 Method and apparatus for constructing an executable program in memory 有权
标题翻译：用于在存储器中构造可执行程序的方法和装置
公开(公告)号：US06907597B1
公开(公告)日：2005-06-14
申请号：US09687322
申请日：2000-10-13
申请人： Andrzej Mamona , Indra Laksono
发明人： Andrzej Mamona , Indra Laksono
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F9/44505
摘要： A method and apparatus for constructing an executable program, such as drivers in memory, obtains system configuration parameters and dynamically constructs driver code bundles from a set of code modules obtained from a library, based on the actual system configuration parameters. The set of code modules includes code modules associated with a plurality of system configuration parameters. One example of the system configuration parameter include static system configuration parameters such as in the case of a computer, a CPU type, clock speed and system memory size. Other actual system configuration parameters include dynamic configuration parameters which can be changed by the user. One example of a dynamic configuration parameter may be, for example, pixel depth and display screen resolution. After obtaining optimal system configuration depending upon a system's setting or configurations, dedicated code modules are used and stored in system memory or other suitable memory. Accordingly, optimal driver code is loaded at all times for a particular chip set and no unnecessary code is loaded from a CD ROM or other source.
摘要翻译：用于构建诸如存储器中的驱动器的可执行程序的方法和装置从基于实际的系统配置参数的库中获得的一组代码模块中获得系统配置参数并动态地构建驱动程序代码束。所述代码模块集合包括与多个系统配置参数相关联的代码模块。系统配置参数的一个示例包括静态系统配置参数，例如在计算机的情况下，CPU类型，时钟速度和系统存储器大小。其他实际的系统配置参数包括用户可以更改的动态配置参数。动态配置参数的一个示例可以是例如像素深度和显示屏幕分辨率。在根据系统的设置或配置获得最佳系统配置后，使用专用代码模块并将其存储在系统存储器或其他合适的存储器中。因此，针对特定芯片组的所有时间都加载了最佳的驱动程序代码，并且没有不必要的代码从CD ROM或其他源加载。

35. 发明授权

US06903739B2 Graphic display system having a frame buffer with first and second memory portions 有权
标题翻译：具有具有第一和第二存储器部分的帧缓冲器的图形显示系统
公开(公告)号：US06903739B2
公开(公告)日：2005-06-07
申请号：US09789074
申请日：2001-02-20
申请人： Stephen L. Morein
发明人： Stephen L. Morein
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/005
摘要： A graphics display system has a graphics processor system for forming a color image on a display, the display being composed of an array of pixels. A memory system has a first memory for storing at least respective color data and respective Z data that is render from primitives of the image, and a second memory for storing respective display data, derived from the rendered color data and Z data, for each of the pixels. The graphics processor system has a memory interface operatively connected to the first and second memories. During formation of an image frame, the memory interface writes to and reads from a Z buffer, and only writes to a render target color buffer. After the image is rendered, image data is copied from the first memory to the second memory from which the image is displayed.
摘要翻译：图形显示系统具有用于在显示器上形成彩色图像的图形处理器系统，该显示器由像素阵列组成。存储器系统具有用于存储至少相应的颜色数据和从图像的图形呈现的相应的Z数据的第一存储器，以及用于存储从渲染的颜色数据和Z数据导出的各个显示数据的第二存储器，像素。图形处理器系统具有可操作地连接到第一和第二存储器的存储器接口。在形成图像帧期间，存储器接口写入和读取Z缓冲器，并且只写入渲染目标色彩缓冲器。在渲染图像之后，将图像数据从第一存储器复制到显示图像的第二存储器。

36. 发明授权

US06850692B1 Method and apparatus for retrieving digital video using successive linear approximation 有权
标题翻译：使用连续线性近似来检索数字视频的方法和装置
公开(公告)号：US06850692B1
公开(公告)日：2005-02-01
申请号：US09471676
申请日：1999-12-23
申请人： Stefan Eckart
发明人： Stefan Eckart
IPC分类号： G11B27/10 , H04N9/804 , H04N5/783
CPC分类号： G11B27/107 , G11B2220/90 , H04N9/8042
摘要： A method and apparatus for successive linear approximation to obtain a specific point on a non-linear monotonic function include processing that begins by obtaining a T-coordinate for the specific point. The specific point includes a T-coordinate and an N-coordinate. The process then continues by selecting a minimum point and a maximum point on the non-linear monotonic function to bound the specific point. The processing then continues by deriving a linear reference between the minimum and maximum points. The process then proceeds by obtaining a reference N-coordinate that lies on the linear reference based on the T-coordinate. The process then continues by determining a reference T-coordinate lying on the non-linear monotonic function based on the referenced N-coordinate. The process then continues by determining whether the referenced T-coordinate is substantially similar to the T-coordinate. When the referenced T-coordinate is not substantially similar to the T-coordinate, re-defining the minimum point or the maximum point based on the referenced T-coordinate. The process then repeats until the referenced T-coordinate is substantially similar to the T-coordinate. Once the referenced T-coordinate is substantially similar to the T-coordinate, the referenced N-coordinate is determined to be substantially equal to the N-coordinate such that the specific point.
摘要翻译：用于连续线性近似以获得非线性单调函数上的特定点的方法和装置包括通过获得特定点的T坐标而开始的处理。具体点包括T坐标和N坐标。然后，该过程通过选择非线性单调函数上的最小点和最大点来结合特定点来继续。然后通过在最小点和最大点之间导出线性参考来继续处理。然后通过基于T坐标获得位于线性参考的参考N坐标来进行该过程。然后通过基于所引用的N坐标确定位于非线性单调函数上的参考T坐标来继续该过程。然后，该过程通过确定所引用的T坐标是否基本上类似于T坐标继续。当所引用的T坐标基本上与T坐标基本相似时，基于所引用的T坐标重新定义最小点或最大点。然后该过程重复，直到所参考的T坐标基本上类似于T坐标。一旦参考的T坐标基本上类似于T坐标，则所参考的N坐标被确定为基本上等于N坐标，使得该特定点。

37. 发明授权

US6081823A Circuit and method for wrap-around sign extension for signed numbers 失效
标题翻译：用于带符号数字的环绕符号扩展的电路和方法
公开(公告)号：US6081823A
公开(公告)日：2000-06-27
申请号：US100266
申请日：1998-06-19
申请人： Stephen C. Purcell , Nital P. Patwa
发明人： Stephen C. Purcell , Nital P. Patwa
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/49994
摘要： A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.
摘要翻译：乘法器具有两个输入值端子，其接收两个带符号的输入位组。乘法器还具有两个输出端子，其被配置为携带以冗余形式表示两个带符号输入值的乘积的和和携带位组。符号确定电路产生表示两个输入有符号值的积的符号的符号位。扩展单元具有三个输入端子，其被配置为接收和位组的最高有效位，进位位组的最高有效位以及由符号确定电路产生的符号位。扩展单元是生成最低有效扩展位和更重要的扩展位的结构。如果最高有效位，符号位和进位最高有效位具有相同的二进制状态，则最低有效扩展位具有一个二进制状态。最不重要的扩展位否则具有相反的二进制状态。

38. 发明授权

US5977836A Method and apparatus for controlling an output frequency of a phase locked loop 失效
标题翻译：用于控制锁相环输出频率的方法和装置
公开(公告)号：US5977836A
公开(公告)日：1999-11-02
申请号：US876731
申请日：1997-06-16
申请人： Philip Lawrence Swan , David Ian James Glen
发明人： Philip Lawrence Swan , David Ian James Glen
IPC分类号： G09G3/20 , H03L7/18 , H03L7/183
CPC分类号： H03L7/18 , G09G3/20
摘要： A method and apparatus for controlling an output frequency of a phase locked loop is accomplished by determining a plurality of divider ratios which are based on an input frequency, parameters, and a desired output frequency. Each of the divider ratios is representative of a ratio between the output frequency and input frequency of the phase locked loop. Having determined the plurality of divider ratios, another determination is subsequently made to determine whether the plurality of divider ratios enable the phase locked loop to produce the output frequency within a given frequency tolerance, i.e., within an allowable error. The determination is based on whether changing the divider ratio from the one of the plurality of ratios to an adjacent ratio causes the output frequency to change more than the allowable error. If so, the plurality of ratios needs to be recalculated based on a change in the input frequency and/or one of the parameters. When the output frequency can be established within the allowable error (i.e., a change from one of the divider ratios to another one produced calculated output frequencies that are within the allowable error), the phase locked loop utilizes one of the plurality of ratios to establish the output frequency. The PLL may further utilize other ratios of the plurality of ratios to finely adjust the output frequency thereby effecting a change on the display update rate.
摘要翻译：通过确定基于输入频率，参数和期望的输出频率的多个分频比来实现用于控制锁相环的输出频率的方法和装置。每个分频比代表了锁相环的输出频率和输入频率之间的比率。在确定了多个分频比之后，随后进行另一确定以确定多个分频比是否允许锁相环产生给定频率容差内的输出频率，即在允许误差范围内。决定是基于将分频比从多个比率中的一个比改变为相邻比率是否使得输出频率变化大于可允许误差。如果是这样，则需要基于输入频率的变化和/或其中一个参数来重新计算多个比率。当输出频率可以在允许误差内建立时（即，从分频比之一到另一个产生计算出的输出频率在可允许误差之内），锁相环使用多个比率之一建立输出频率。 PLL可以进一步利用多个比率的其他比率来精细地调整输出频率，从而实现显示更新率的改变。

39. 发明申请

US20080216073A1 Apparatus for executing programs for a first computer architechture on a computer of a second architechture 有权
标题翻译：用于在第二建筑物的计算机上执行用于第一计算机建筑物的程序的装置
公开(公告)号：US20080216073A1
公开(公告)日：2008-09-04
申请号：US11904007
申请日：2007-09-25
申请人： John S. Yates , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
发明人： John S. Yates , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
IPC分类号： G06F9/46
CPC分类号： G06F9/45554 , G06F9/30174 , G06F9/30189 , G06F9/3861
摘要： Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.
摘要翻译：在第二不同架构的计算机上执行以第一计算机的指令集编码的程序。操作系统维护一组并发线程中的每一个与线程上下文的一组计算机资源之间的关联。在不修改计算机的预先存在的操作系统的情况下，将在指定的入口点或指定条件下建立要在操作系统的每个条目上提出的入口异常。条目异常具有相关联的条目处理程序，其被编程为在将修改的上下文传送到操作系统之前，保存中断的线程的上下文并修改线程上下文。在操作系统的每次恢复之后建立恢复异常，补充指定条目之一。恢复异常具有相关联的退出处理程序，其被编程为恢复由相应执行的条目处理程序保存的上下文。入口异常，退出异常，条目处理程序和退出处理程序被协调地设计为通过由操作系统引发的上下文变化来维护线程中的一个线程和线程的扩展上下文之间的关联，扩展的上下文包括与线程相关联的计算机超出与该线程的关联的那些资源由操作系统维护。

40. 发明授权

US07224364B1 Optimal initial rasterization starting point 有权
标题翻译：最佳初始光栅化起始点
公开(公告)号：US07224364B1
公开(公告)日：2007-05-29
申请号：US09244270
申请日：1999-02-03
申请人： Lordson L. Yue , James T. Battle
发明人： Lordson L. Yue , James T. Battle
IPC分类号： G06T11/00 , G06T11/20
CPC分类号： G06T15/005
摘要： A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.
摘要翻译：帧缓冲器被划分为例如32×32像素的瓦片。在给定瓦片内的三角形（及其部分）一次被一个三角形光栅化到瓦片位置。该过程对于图像帧中的每个图块重复。排序电路产生表示当前三角形的顶点的垂直顺序的控制位。一系列多路复用器将这些控制位上的顶点垂直排列。区域计算电路产生表示相对于当前瓦片的每个顶点的位置的区域位。如果区域位指示整个三角形位于瓦片之外，则会发生三角形数据的平凡丢弃。随后，基于区域比特来估计初始光栅化起始点，以降低光栅化器找到要分配值的当前三角形的第一像素所需的时间。

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