专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06784822B1 Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors 有权
公开(公告)号：US06784822B1
公开(公告)日：2004-08-31
申请号：US10693215
申请日：2003-10-24
申请人： Michael A. Nix , Ahmed Younis
发明人： Michael A. Nix , Ahmed Younis
IPC分类号： H03M138
CPC分类号： H03M1/16 , H03M1/60
摘要： A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

22. 发明授权

US06717542B2 Analog to digital converter 有权
标题翻译：模数转换器
公开(公告)号：US06717542B2
公开(公告)日：2004-04-06
申请号：US10263658
申请日：2002-10-04
申请人： Hisashi Harada
发明人： Hisashi Harada
IPC分类号： H03M138
CPC分类号： H03M1/0697 , H03M1/462
摘要： In a conversion sequence for converting an analog input voltage into a digital signal, a redundant comparison cycle is provided to comparison cycles for performing a prescribed number of times of comparison. This redundant comparison cycle may be added after the prescribed number of comparison cycles, or may be inserted into a normal comparison cycle. Such a redundant comparison cycle adds a convergence period of a converted value to the analog input voltage. Accordingly, the final conversion result can be accurately generated even if an error is generated in the conversion sequence. As a result, a successive approximation type analog to digital converter capable of rapidly performing analog-to-digital conversion with high accuracy is implemented.
摘要翻译：在用于将模拟输入电压转换为数字信号的转换序列中，提供冗余比较周期用于执行规定次数的比较的比较周期。该冗余比较循环可以在规定数量的比较循环之后添加，或者可以被插入到正常的比较循环中。这种冗余比较周期将转换后的值的收敛周期添加到模拟输入电压。因此，即使在转换序列中产生错误，也能够精确地生成最终转换结果。结果，实现了能够以高精度快速执行模数转换的逐次逼近型模数转换器。

23. 发明授权

US06703961B2 Serial interface for an analog to digital converter and a converter including such an interface 有权
标题翻译：用于模数转换器的串行接口和包括这种接口的转换器
公开(公告)号：US06703961B2
公开(公告)日：2004-03-09
申请号：US10128033
申请日：2002-04-23
申请人： Michael Mueck , David Gerrard Laing , Alain Valentin Guery
发明人： Michael Mueck , David Gerrard Laing , Alain Valentin Guery
IPC分类号： H03M138
CPC分类号： G06F3/05
摘要： An analog to digital converter is provided which has a compact serial interface utilising only four pins to define chained and non chained modes of operation. Further more the interface also allows the converter to be configured to indicate immediately that the conversion has been completed. Another variant of the invention enables an analog to digital converter to be provided having only a 3 pin serial interface.
摘要翻译：提供了一种模数转换器，其具有仅使用四个引脚的紧凑串行接口来定义链接和非链接操作模式。此外，接口还允许将转换器配置为立即指示转换已完成。本发明的另一变型使得能够提供仅具有3针串行接口的模数转换器。

24. 发明授权

US06504500B1 A/D converter and A/D converting method 失效
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US06504500B1
公开(公告)日：2003-01-07
申请号：US09712208
申请日：2000-11-15
申请人： Sanroku Tsukamoto
发明人： Sanroku Tsukamoto
IPC分类号： H03M138
CPC分类号： H03M1/44
摘要： An A/D converter includes a bit cell for converting an analog input signal to a single-bit digital signal. The bit cell includes an operational circuit for performing at least one of a first operation (Vin−VRH)+(Vin−VRL) and a second operation (VRH−Vin)+(VRL−Vin), where VRH is a high potential reference voltage, VRL is a low potential reference voltage and Vin is the analog input signal.
摘要翻译： A / D转换器包括用于将模拟输入信号转换为单位数字信号的位单元。位单元包括用于执行第一操作（Vin-VRH）+（Vin-VRL）和第二操作（VRH-Vin）+（VRL-Vin））中的至少一个的操作电路，其中VRH是高电位参考电压，VRL是低电位参考电压，Vin是模拟输入信号。

25. 发明授权

US06424284B1 Baseband receiver including dual port DAC 有权
标题翻译：基带接收器包括双端口DAC
公开(公告)号：US06424284B1
公开(公告)日：2002-07-23
申请号：US09653570
申请日：2000-08-31
申请人： Douglas D. Lopata , Malcolm Harold Smith
发明人： Douglas D. Lopata , Malcolm Harold Smith
IPC分类号： H03M138
CPC分类号： H04B1/0032 , H03M1/46 , H03M1/662 , H03M1/765 , H04B1/0003 , H04B1/30
摘要： A baseband receiver particularly well-suited for wireless applications utilizes a dual-port DAC in a successive-approximation ADC, where the dual-port DAC replaces the separate pair of single port conventional DACs and is therefore shared by the I and Q down-converted components. The use of a dual-port DAC results in significant size and power savings over conventional arrangements.
摘要翻译：特别适用于无线应用的基带接收器在逐次逼近ADC中使用双端口DAC，其中双端口DAC替代单独的一对单端口常规DAC，因此由I和Q下转换组件。与常规布置相比，双端口DAC的使用导致显着的尺寸和功率节省。

26. 发明授权

US06337651B1 Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage 有权
标题翻译：管道模拟数字（A / D）转换器，对采样和保持级具有放宽的精度要求
公开(公告)号：US06337651B1
公开(公告)日：2002-01-08
申请号：US09506284
申请日：2000-02-17
申请人： Meei-Ling Chiang
发明人： Meei-Ling Chiang
IPC分类号： H03M138
CPC分类号： H03M1/442 , H03M1/0695
摘要： A pipeline analog to digital (A/D) converter. The pipeline A/D converter having a sample and hold amplifier stage, the sample and hold amplifier stage sampling an analog input signal during a first clock pulse signal. The pipeline A/D converter having an analog signal converter stage, the analog signal converter stage sampling the analog input signal during a first clock pulse signal. According to another aspect of the invention, the pipeline A/D converter converts an analog input signal into a digital representation of the analog input signal. The pipeline A/D converter has a clock generator, the clock generator generating a first clock pulse signal, a second clock pulse signal and a third clock pulse signal. A sample and hold stage samples an analog input signal during the pulse of the first clock signal and holds a sampled voltage signal during the pulse of the second clock signal. A first analog signal converter stage converts and latches the sampled and held voltage signal into a digital output during the pulse of the second clock signal, a most significant bit of the digital representation of the analog input signal being derived from the digital output. The first analog signal converter stage generating a residue signal based on a comparison of the analog input signal and from an analog representation of the digital output. The first analog signal converter stage sampling the analog input signal during the pulse of the first clock signal and holding the residue signal during the pulse of the third clock signal.
摘要翻译：一种管线模数（A / D）转换器。具有采样和保持放大器级的流水线A / D转换器，采样和保持放大器级在第一时钟脉冲信号期间对模拟输入信号进行采样。具有模拟信号转换器级的管线A / D转换器，模拟信号转换器级在第一时钟脉冲信号期间对模拟输入信号进行采样。根据本发明的另一方面，流水线A / D转换器将模拟输入信号转换为模拟输入信号的数字表示。管线A / D转换器具有时钟发生器，时钟发生器产生第一时钟脉冲信号，第二时钟脉冲信号和第三时钟脉冲信号。采样和保持级在第一时钟信号的脉冲期间采样模拟输入信号，并且在第二时钟信号的脉冲期间保持采样的电压信号。第一模拟信号转换器级在第二时钟信号的脉冲期间将采样和保持的电压信号转换并锁存为数字输出，模拟输入信号的数字表示的最高有效位是从数字输出导出的。第一模拟信号转换器级基于模拟输入信号与数字输出的模拟表示的比较产生残留信号。第一模拟信号转换器级在第一时钟信号的脉冲期间对模拟输入信号进行采样，并在第三时钟信号的脉冲期间保持残留信号。

27. 发明授权

US06304204B1 Error correction architecture for pipeline analog to digital converters 有权
标题翻译：管道模数转换器的纠错架构
公开(公告)号：US06304204B1
公开(公告)日：2001-10-16
申请号：US09546992
申请日：2000-04-11
申请人： Orhan Norman
发明人： Orhan Norman
IPC分类号： H03M138
CPC分类号： H03M1/069 , H03M1/44
摘要： A pipeline analog to digital converter architecture includes at least two error correction stages, one such error correction stage at the end of the pipeline architecture such that power savings and silicon area optimization are achieved by tailoring the performance of the pipeline stages towards the end of the pipeline architecture. The other error correction stages are placed with respect to the overall design sensitivities. The design according to the present invention is applicable to a broad class of pipeline architectures including multi-bit stages in the pipeline architecture.
摘要翻译：管线模数转换器架构包括至少两个误差校正级，在流水线架构结束时的一个这样的纠错级，从而通过将流水线级的性能定制为最终，实现功率节省和硅面积优化管道架构。相对于整体设计灵敏度放置其他纠错阶段。根据本发明的设计可应用于包括流水线架构中的多位阶段的广泛类型的流水线结构。

28. 发明授权

US06218976B1 Analog-to-digital converter with successive approximation 失效
标题翻译：具有逐次逼近的模数转换器
公开(公告)号：US06218976B1
公开(公告)日：2001-04-17
申请号：US09293884
申请日：1999-04-19
申请人： Jan-Erik Eklund , Anders Edman
发明人： Jan-Erik Eklund , Anders Edman
IPC分类号： H03M138
CPC分类号： H03M1/0695 , H03M1/38
摘要： A process and device for providing an analog-to-digital conversion employing a successive approximation principle is provided. The search interval from a value X to a Value Y, which represents the value interval in which an unknown analog signal is to be converted to a digital signal value, is divided into a number of smaller search intervals, being divided into different area for employing a successive approximation process to iterate to the desired digital signal value. Further, reference levels are defined for each search interval to coincide with at least one other reference level, where coinciding reference level belongs to two search intervals formed by areas in a nearest larger search interval.
摘要翻译：提供了一种使用逐次逼近原理提供模数转换的处理和装置。从值X到值Y的搜索间隔被划分成较小的搜索间隔的数量，该值Y表示未知模拟信号要转换为数字信号值的值间隔，被划分为不同的区域用于采用逐次逼近处理以迭代到期望的数字信号值。此外，为每个搜索间隔定义参考水平以与至少一个其他参考水平一致，其中一致的参考水平属于由最近较大的搜索间隔中的区域形成的两个搜索间隔。

29. 发明授权

US06181268B2 Successive approximation A/D converter improving tracking ability of digital signal to analog signal 失效
标题翻译：逐次逼近A / D转换器提高数字信号到模拟信号的跟踪能力
公开(公告)号：US06181268B2
公开(公告)日：2001-01-30
申请号：US09287567
申请日：1999-04-06
申请人： Takashi Miyake , Yoshikazu Sato
发明人： Takashi Miyake , Yoshikazu Sato
IPC分类号： H03M138
CPC分类号： H03M1/46
摘要： A successive approximation A/D converter which converts an analog signal to a digital signal by carrying out successive A/D conversions of the analog signal. It carries out, for a least significant bit of the digital signal, A/D conversion of the analog signal using a reference voltage corresponding to a previous digital signal obtained as a result of a previous A/D conversion, increments a current digital signal, which is obtained as a result of the latest A/D conversion, when the least significant bit of the current digital signal is “1”, and decrements the current digital signal when the least significant bit is “0”. This makes it possible to solve a problem of a conventional successive approximation A/D converter in that the tracking ability of the digital signal to variations of the analog signal is degraded because of the long update period involved in the increasing number of the bits of the A/D converter, if full bit conversion is carried out.
摘要翻译：逐次逼近A / D转换器，其通过执行模拟信号的连续A / D转换将模拟信号转换为数字信号。它对于数字信号的最低有效位执行使用与作为先前A / D转换的结果获得的先前数字信号相对应的参考电压的模拟信号的A / D转换，增加当前的数字信号，当当前数字信号的最低有效位为“1”时，作为最新的A / D转换的结果获得的，当最低有效位为“0”时，该值减小当前的数字信号。这使得可以解决传统的逐次逼近A / D转换器的问题在于，数字信号对模拟信号的变化的跟踪能力由于在增加的位数增加所涉及的较长的更新周期而降低如果进行全位转换，则A / D转换器。

30. 发明授权

US06753801B2 Fully differential reference driver for pipeline analog to digital converter 有权
标题翻译：用于管道模数转换器的全差分参考驱动器
公开(公告)号：US06753801B2
公开(公告)日：2004-06-22
申请号：US10226018
申请日：2002-08-23
申请人： Giuseppe Rossi
发明人： Giuseppe Rossi
IPC分类号： H03M138
CPC分类号： H03F3/005 , H03F2200/331 , H03M1/38
摘要： An analog to digital conversion (ADC) circuit is disclosed including a fully differential reference voltage source. The reference voltage source includes a programmable current supply adapted to drive a programmed current through a resistor so as to establish an initial reference voltage. The initial reference voltage is sampled onto a capacitive network during a first sampling time interval. The capacitive network is coupled to a differential input of a fully differential amplifier, and maintained at a differential output of the differential amplifier during a second output time interval. An output coupling between the differential output and differential input of the differential amplifier acts to maintain stability of the output voltage during the output time interval.
摘要翻译：公开了一种模数转换（ADC）电路，其包括全差分参考电压源。参考电压源包括可编程电流源，其适于驱动通过电阻器的编程电流，以便建立初始参考电压。在第一采样时间间隔期间，将初始参考电压采样到电容网络上。电容网络耦合到全差分放大器的差分输入，并且在第二输出时间间隔期间保持在差分放大器的差分输出。差分放大器的差分输出和差分输入之间的输出耦合用于在输出时间间隔期间保持输出电压的稳定性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式