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21. 发明申请

US20050081858A1 Mask assembly 有权
标题翻译：面具组装
公开(公告)号：US20050081858A1
公开(公告)日：2005-04-21
申请号：US10961091
申请日：2004-10-12
申请人： Milind Raje , Timothy Fu , Amal Amarasinghe , Joanne Drew , Robert Frater , Memduh Guney , Clive Solari
发明人： Milind Raje , Timothy Fu , Amal Amarasinghe , Joanne Drew , Robert Frater , Memduh Guney , Clive Solari
IPC分类号： A61M16/06 , A61M16/08 , H03K5/05 , H03K5/151 , H03K7/04 , A62B18/02 , A62B18/08
CPC分类号： A61M16/0616 , A61M16/06 , A61M16/0611 , A61M16/0622 , A61M16/0633 , A61M16/0638 , A61M16/065 , A61M16/0655 , A61M16/0683 , A61M16/08 , A61M16/0825 , A61M16/085 , A61M16/0858 , A61M16/0875 , A61M2205/42 , A61M2206/14
摘要： A respiratory mask assembly for use in the delivery of non-invasive positive airway pressure to a user. The assembly includes a rigid shell having a channel portion defined by an inner wall, an outer wall and a channel floor, a face-contacting cushion acting to space the shell away from the user's face and a sealing tab extending from the cushion to engage a portion of the shell to provide a continuous airtight seal between the cushion and the shell. A retaining ring within the mask assembly is configured to secure the cushion to the shell. The retaining ring has a first portion including at least one clip configured to pass through at least one slot portion such that an underside surface of the at least one clip engages a section of the shell when the retaining ring is positioned within the channel.
摘要翻译：一种呼吸面罩组件，用于向使用者输送非侵入性正压通气。组件包括刚性壳体，其具有由内壁，外壁和通道底板限定的通道部分，用于将壳体远离使用者面部的面接触垫片以及从衬垫延伸以接合的密封片壳体的一部分以在衬垫和壳体之间提供连续的气密密封。掩模组件内的保持环被构造成将衬垫固定到壳体上。保持环具有第一部分，其包括构造成穿过至少一个狭槽部分的至少一个夹子，使得当保持环定位在通道内时，至少一个夹子的下侧表面接合壳体的一部分。

22. 发明申请

US20050017781A1 Complementary signal generator 失效
标题翻译：互补信号发生器
公开(公告)号：US20050017781A1
公开(公告)日：2005-01-27
申请号：US10779649
申请日：2004-02-18
申请人： Takashi Honda
发明人： Takashi Honda
IPC分类号： H03K5/12 , H03K5/151
CPC分类号： H03K5/151
摘要： A complementary signal generator, for outputting complementary positive-phase and antiphase signals that vary between a first logical value and a second logical value, which includes a signal forming unit for outputting a positive-phase intermediate signal being in phase with an input signal varying between the first logical value and the second logical value, and an antiphase intermediate signal antiphase to the input signal. The generator also includes a first connecting means for simultaneously transferring the second logical value of the positive-phase intermediate signal and the first logical value of the antiphase intermediate signal to a positive-phase signal output part and an antiphase signal output part in synchronism with a state change of the input signal from the first logical value to the second logical value.
摘要翻译：一种互补信号发生器，用于输出在第一逻辑值和第二逻辑值之间变化的互补正相和反相信号，该信号包括用于输出正相中间信号的信号形成单元，该正相中间信号与第一逻辑值和第二逻辑值，以及反相中间信号反相到输入信号。发电机还包括第一连接装置，用于同步地将正相中间信号的第二逻辑值和反相中间信号的第一逻辑值同时传送到正相信号输出部分和反相信号输出部分将输入信号从第一逻辑值状态改变为第二逻辑值。

23. 发明授权

US06842040B1 Differential interconnection circuits in programmable logic devices 有权
标题翻译：可编程逻辑器件中的差分互连电路
公开(公告)号：US06842040B1
公开(公告)日：2005-01-11
申请号：US10319329
申请日：2002-12-13
申请人： Wanli Chang , Andy Lee , Cameron McClintock , Richard Cliff , Richard Yen-Hsiang Chang
发明人： Wanli Chang , Andy Lee , Cameron McClintock , Richard Cliff , Richard Yen-Hsiang Chang
IPC分类号： H03K5/151 , H03K19/017 , H03K19/177
CPC分类号： H03K19/17736 , H03K5/151 , H03K19/01721 , H03K19/17784
摘要： At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.
摘要翻译：可编程逻辑器件（“PLD”）上的至少一些互连信号通过使用差分驱动器电路的差分信号来将差分信号施加到延伸到差分接收器电路的一对导体。这种差分互连信令有助于PLD在较低的电源电压下令人满意地工作。每个差分信号对中的导体可以以不同的间隔彼此交叉，以便有助于减少相邻和并行信令路径之间的电容耦合的不利影响。

24. 发明授权

US06838922B2 Circuit arrangement for generating non-overlapping clock phases 失效
标题翻译：用于产生非重叠时钟相位的电路布置
公开(公告)号：US06838922B2
公开(公告)日：2005-01-04
申请号：US10789959
申请日：2004-02-27
申请人： Gebhard Melcher
发明人： Gebhard Melcher
IPC分类号： H03K5/15 , H03K5/151 , G06F1/04
CPC分类号： H03K5/1504 , H03K5/1515
摘要： A circuit arrangement for generating non-overlapping clock phases including a first circuit, a second circuit, and a multiplexer. The first circuit combines two input signals to form an output signal, and a first input provides for application of a common clock signal. The second circuit combines two input signals to form an output signal, and a first input provides for application of the common clock signal. The multiplexer has a first input connected to an output of the first circuit, a second input connected to an output of the second circuit, and an output connected to a second input of each of the first and second circuits, and has a third input that switches between the first and second inputs of the multiplexer for application of the clock signal. A plurality of non-overlapping clock phases are provided by output signals of the first and second circuits and of the multiplexer.

25. 发明授权

US6150879A Semiconductor apparatus for use in low voltage power supply 失效
标题翻译：用于低压电源的半导体装置
公开(公告)号：US6150879A
公开(公告)日：2000-11-21
申请号：US154713
申请日：1998-09-17
申请人： Daita Watanabe
发明人： Daita Watanabe
IPC分类号： H02H7/20 , H02M3/07 , H03K5/151 , H03L7/08 , H03L7/089 , H03L7/18 , H03K7/162
CPC分类号： H02M3/07 , H03K5/1515 , H03L7/08 , H03L7/0802 , H03L7/0891 , H03L7/18
摘要： A semiconductor apparatus for use with a low voltage power supply includes an internal circuit that operates in synchronization with a first clock signal that is input from an external terminal or generated by a clock generating circuit, a voltage raising circuit for raising a power supply voltage in synchronization with a second clock signal whose pulse edge does not overlap with that of the first clock signal, and a constant voltage circuit for inputting an output voltage of the voltage raising circuit and supplying a constant voltage as a power supply voltage to the internal circuit.
摘要翻译：与低电压电源一起使用的半导体装置包括内部电路，其与从外部端子输入或由时钟发生电路产生的第一时钟信号同步操作，用于提高电源电压的升压电路与其脉冲边缘与第一时钟信号不重叠的第二时钟信号同步;以及恒压电路，用于输入升压电路的输出电压并将恒定电压作为电源电压提供给内部电路。

26. 发明授权

US06121809A Accurate and tuneable active differential phase splitters in RFIC wireless applications 有权
标题翻译： RFIC无线应用中精确和可调谐的有源差分相位分离器
公开(公告)号：US06121809A
公开(公告)日：2000-09-19
申请号：US270906
申请日：1999-03-15
申请人： Huainan Ma , Sher Jiun Fang , Fujiang Lin
发明人： Huainan Ma , Sher Jiun Fang , Fujiang Lin
IPC分类号： H03F3/26 , H03K5/151 , H03K5/13
CPC分类号： H03K5/151 , H03F3/265
摘要： A differential phase splitter circuit for producing opposite phase signals from an input AC signal is provided. A first and second transistor is provided. The source of these transistors are connected to a common first node. Further, these transistors act as a differential amplifier. The gate of the first transistor receives an input AC signal. The drain of the first transistor produces a first output AC signal. Similarly, the drain of the second transistor produces a second output AC signal that is 180 degrees out of phase with the first output AC signal. A source resistor is provided, connected in series to the common first node and ground. Lastly, an LCR feedback circuit is provided. This feedback circuit is connected between the drain of the first transistor and the gate of the second transistor. The LCR feedback circuit couples at least a fraction of the amplitude of the first output AC signal to the gate of the second transistor for amplitude balancing and phase balancing. This compensates for an unequal division of the input signal between the first and second transistor due to the finite impedance value of the source resistor. The LCR feedback circuit may include an active element for modifying the phase and amplitude balance of the two output AC signals. The active element may be adjusted using a control voltage.
摘要翻译：提供了用于从输入AC信号产生相反相位信号的差分相位分离器电路。提供第一和第二晶体管。这些晶体管的源极连接到公共第一节点。此外，这些晶体管用作差分放大器。第一晶体管的栅极接收输入AC信号。第一晶体管的漏极产生第一输出AC信号。类似地，第二晶体管的漏极产生与第一输出AC信号180度异相的第二输出AC信号。提供源电阻，串联连接到公共第一节点和地。最后，提供LCR反馈电路。该反馈电路连接在第一晶体管的漏极和第二晶体管的栅极之间。 LCR反馈电路将第一输出AC信号的幅度的至少一部分耦合到第二晶体管的栅极用于幅度平衡和相位平衡。这由于源极电阻的有限阻抗值而补偿了第一和第二晶体管之间的输入信号的不相等。 LCR反馈电路可以包括用于修改两个输出AC信号的相位和幅度平衡的有源元件。可以使用控制电压来调节有源元件。

27. 发明授权

US06069498A Clock generator for CMOS circuits with dynamic registers 失效
标题翻译：具有动态寄存器的CMOS电路的时钟发生器
公开(公告)号：US06069498A
公开(公告)日：2000-05-30
申请号：US945725
申请日：1997-11-05
申请人： Tobias Noll , Stefan Meier , Matthias Schobinger , Erik De Man
发明人： Tobias Noll , Stefan Meier , Matthias Schobinger , Erik De Man
IPC分类号： G06F1/04 , G11C7/22 , H03K5/151 , H03K5/153 , H03K5/19 , H03K9/06
CPC分类号： H03K5/153 , G11C7/22 , H03K5/19
摘要： An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.
摘要翻译： PCT No.PCT / DE96 / 00794 Sec。 371日期：1997年11月5日 102（e）日期1997年11月5日PCT提交1996年5月7日PCT公布。 WO96 / 36113 PCT出版物日期：1996年11月14日装置具有时钟监视装置，其确定输入时钟信号（PHI 0）的时钟速率是否已经低于预定的最小时钟速率。提供了一种系统，其从输入时钟信号形成主时钟信号（PHI m）和从时钟信号（PHI s），其形式使得动态主机寄存器（ML）的两个开关（S1）并且动态从属寄存器（SL）的开关（S2）关闭，只要时钟速率已经低于最小时钟速率。否则，动态从动锁存器（SL）的动态主锁存器（ML）或开关（S2）中的至少一个开关（S1）关闭。所实现的主要优点是，在输入时钟信号失效的情况下，特别是在具有高流水线流量的电路中，未定义的寄存器状态不会导致不允许的高电流消耗。

28. 发明授权

US5966037A Method for manufacturing an integrated circuit with programmable non-overlapping-clock-edge capability 失效
标题翻译：用于制造具有可编程非重叠时钟边缘能力的集成电路的方法
公开(公告)号：US5966037A
公开(公告)日：1999-10-12
申请号：US795363
申请日：1997-02-04
申请人： Ho Dai Truong , Chong Ming Lin
发明人： Ho Dai Truong , Chong Ming Lin
IPC分类号： H03K5/151 , H03K3/037
CPC分类号： H03K5/1515 , H03K2005/00058
摘要： A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.
摘要翻译：一种用于使用独特的可编程片上时钟发生器在芯片上产生和优化具有非重叠边沿的时钟信号的系统和方法。通过调整片上时钟发生器电路中引入的延迟量来避免时钟信号边沿的重叠。通过使用硬件和/或软件编程对片上时钟发生器进行编程来调整延迟量。在硬件编程中，通过物理上改变片上时钟发生器中的延迟元件的组成来调整延迟量。在软件编程中，使用软件命令调整延迟，以控制片内时钟发生器中的延迟元件的操作，或选择延迟信号的路径。

29. 发明授权

US5936893A Integrated circuit clock input buffer 失效
公开(公告)号：US5936893A
公开(公告)日：1999-08-10
申请号：US109632
申请日：1998-07-02
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/10 , G11C7/22 , H03K5/151 , G11C7/00
CPC分类号： G11C7/225 , G11C7/1072 , G11C7/22 , H03K5/151
摘要： An integrated circuit clock buffer is described which includes output circuits for generating internal clock signals in response to an externally provided clock signal. The clock buffer includes a latch circuit having a delayed feedback to provide a pulsed signal in response to a transition in the external clock signal. The output circuits have a trip point which is skewed in one direction to detect a rising transition of the pulsed signal, and are skewed in a second direction to detect a falling transition of the pulsed signal. The buffer generates two non-skewed internal clock signals which have sharp rising and falling transitions.

30. 发明授权

US5812832A Digital clock waveform generator and method for generating a clock signal 失效
标题翻译：数字时钟波形发生器和用于产生时钟信号的方法
公开(公告)号：US5812832A
公开(公告)日：1998-09-22
申请号：US011068
申请日：1993-01-29
申请人： Stephen C. Horne , Scott H. R. McMahon
发明人： Stephen C. Horne , Scott H. R. McMahon
IPC分类号： H03K5/151 , G06F1/04 , H03K5/156 , G06F1/08
CPC分类号： H03K5/1565 , G06F1/04
摘要： A digital clock waveform generator and method for generating a clock signal are provided for a microprocessor or other digital circuit to provide on chip generation of internal clock signals having the same frequency as or a higher or lower frequency than an externally applied clock signal. In one embodiment, the waveform generator includes a delay chain and a control unit that matches the propagation delay of the delay chain to the period of an input timing signal. The waveform generator provides precise control of the duty cycles of the internally generated clock signals, and allows for rapid starting and stopping of the internal clock signals for power reduction functions. The waveform generator may further provide a system clock, and may include circuitry to precisely control the phase relationships between the various clock signals. The waveform generator is easily manufactured with digital circuitry that automatically compensates for changing environmental conditions such as operating voltage and temperature.
摘要翻译：提供了一种用于产生时钟信号的数字时钟波形发生器和方法，用于微处理器或其它数字电路，以提供具有与外部施加的时钟信号相同频率或更高或更低频率的内部时钟信号的片上产生。在一个实施例中，波形发生器包括延迟链和控制单元，其将延迟链的传播延迟与输入定时信号的周期相匹配。波形发生器可精确控制内部产生的时钟信号的占空比，并允许快速启动和停止用于功耗降低功能的内部时钟信号。波形发生器还可以提供系统时钟，并且可以包括用于精确控制各种时钟信号之间的相位关系的电路。波形发生器易于制造，数字电路可自动补偿不断变化的环境条件，如工作电压和温度。

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