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21. 发明授权

US11637201B2 Insulated gated field effect transistor structure having shielded source and method 有权
公开(公告)号：US11637201B2
公开(公告)日：2023-04-25
申请号：US17456266
申请日：2021-11-23
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Xiaoli Wu , Joseph Andrew Yedinak
IPC分类号： H01L29/78 , H01L27/07 , H01L29/10
摘要： A semiconductor device includes a region of semiconductor material of a first conductivity type and having a first major surface. A body region of a second conductivity type opposite to the first conductivity type is in the region of semiconductor material. The body region includes a stripe region; a first segment in the stripe region and having a first peak dopant concentration, a first depth into the region of semiconductor material, and a first length along the first major surface; and a second segment in the stripe region laterally adjacent to the first segment, adjacent to the first major surface, and having a second peak dopant concentration, a second depth into the region of semiconductor material, and a second length along the first major surface. A source region of the first conductivity type is in the first segment but not in at least part of the second segment. An insulated gate electrode adjoins the first segment and is configured to provide a first channel region in the first segment, adjoins the second segment and configured to provide a second channel region in the second segment, and adjoins the first source region. A conductive structure is connected to the first segment, the second segment, and the source region. During a linear mode of operation, current flows first in the second segment but not in the first segment to reduce the likelihood of thermal runaway.

22. 发明授权

US11637200B2 Power semiconductor device 有权
公开(公告)号：US11637200B2
公开(公告)日：2023-04-25
申请号：US17378820
申请日：2021-07-19
申请人： UNITED MICROELECTRONICS CORP.
发明人： Zong-Han Lin , Yi-Han Ye
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/06
摘要： A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

23. 发明授权

US11637193B2 Gate-all-around field effect transistor and method for manufacturing same 有权
公开(公告)号：US11637193B2
公开(公告)日：2023-04-25
申请号：US17015270
申请日：2020-09-09
申请人： Semiconductor Manufacturing International (Beijing) Corporation , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
发明人： Poren Tang
IPC分类号： H01L29/78 , H01L29/66 , H01L21/306 , H01L29/08 , H01L29/06 , H01L29/423 , H01L29/786
摘要： This application discloses a gate-all-around field effect transistor and a method for manufacturing same. In some implementations the method may include: forming a first fin structure on a substrate, where each first fin structure includes one first laminated structure, where the first laminated structure sequentially includes a sacrificial layer, a support layer, and a channel layer from bottom to top; forming a dummy gate structure across the first fin structure, where the dummy gate structure includes a dummy gate dielectric layer, a dummy gate on the dummy gate dielectric layer, and a first spacer on a side surface of the dummy gate; removing parts of the first fin structure located on two sides of the dummy gate structure, to form a second fin structure; performing first etching on a side surface of the sacrificial layer in the second fin structure, to form a first space; forming a second spacer in the first space; performing second etching on a side surface of the channel layer in the second fin structure, to form a second space; and performing selective epitaxy on the side surface of the channel layer in the second fin structure, to form a source region and a drain region, where along a direction of a channel, compared with a side surface, distal to the sacrificial layer, of the second spacer, the side surface of the channel layer after the second etching is closer to the sacrificial layer.

24. 发明授权

US11637191B2 Piezo-resistive transistor based resonator with ferroelectric gate dielectric 有权
公开(公告)号：US11637191B2
公开(公告)日：2023-04-25
申请号：US16238420
申请日：2019-01-02
申请人： Intel Corporation
发明人： Tanay Gosavi , Chia-ching Lin , Raseong Kim , Ashish Verma Penumatcha , Uygar Avci , Ian Young
IPC分类号： H01L29/51 , H01L29/78 , H01L27/088 , H03H9/17 , H01L29/423
摘要： Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

25. 发明授权

US11637188B2 Non-volatile memory device and method for fabricating the same 有权
公开(公告)号：US11637188B2
公开(公告)日：2023-04-25
申请号：US17226431
申请日：2021-04-09
申请人： UNITED MICROELECTRONICS CORP.
发明人： Yu-Jen Yeh , Chih-Jung Chen
IPC分类号： H10B41/30 , H01L29/423 , H01L27/11521 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/788 , H01L21/265 , H01L21/28
摘要： An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

26. 发明授权

US11637179B2 Airgap vertical transistor without structural collapse 有权
公开(公告)号：US11637179B2
公开(公告)日：2023-04-25
申请号：US17131904
申请日：2020-12-23
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Chanro Park , Juntao Li , Ruilong Xie
IPC分类号： H01L29/06 , H01L21/768 , H01L27/088 , H01L29/78 , H01L21/764 , H01L21/762 , H01L21/311 , H01L21/8234 , H01L21/8238 , H01L29/66
摘要： Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.

27. 发明授权

US11637065B2 Semiconductor device including via and wiring 有权
公开(公告)号：US11637065B2
公开(公告)日：2023-04-25
申请号：US17648829
申请日：2022-01-25
申请人： Samsung Electronics Co., Ltd.
发明人： Miji Lee , Taeyoung Jeong , Yoonkyeong Jo , Sangwoo Pae , Hwasung Rhee
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L23/532 , H01L29/417 , H01L29/78
摘要： A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

28. 发明授权

US11637018B2 Barrier layer for contact structures of semiconductor devices 有权
公开(公告)号：US11637018B2
公开(公告)日：2023-04-25
申请号：US17081738
申请日：2020-10-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Hsinhsiang Tseng , Chi-Ruei Yeh , Tsung-Yu Chiang
IPC分类号： H01L21/285 , H01L21/3213 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/78
摘要： The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

29. 发明申请

US20230124471A1 FINFET HAVING A GATE DIELECTRIC COMPRISING A MULTI-LAYER STRUCTURE INCLUDING AN OXIDE LAYER WITH DIFFERENT THICKNESSES ON SIDE AND TOP SURFACES OF THE FINS 有权
公开(公告)号：US20230124471A1
公开(公告)日：2023-04-20
申请号：US18083576
申请日：2022-12-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chen-Hsuan Liao , Chih-Chung Chang , Chun-Heng Chen , Jiun-Ming Kuo
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L21/28 , H01L21/8234
摘要： A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

30. 发明申请

US20230123670A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE 有权
公开(公告)号：US20230123670A1
公开(公告)日：2023-04-20
申请号：US18068257
申请日：2022-12-19
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wei-Siang YANG , Ming-Hua YU
IPC分类号： H01L29/66 , H01L27/092 , H01L21/8234 , H01L29/78
摘要： Semiconductor devices and methods of forming semiconductor devices are described herein. A method includes forming a first fin and a second fin in a substrate. A low concentration source/drain region is epitaxially grown over the first fin and over the second fin. The material of the low concentration region has less than 50% by volume of germanium. A high concentration contact landing region is formed over the low concentration regions. The material of the high concentration contact landing region has at least 50% by volume germanium. The high concentration contact landing region has a thickness of at least 1 nm over a top surface of the low concentration source/drain region.

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