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21. 发明申请

US20040034725A1 One shot RDMA having a 2-bit state 有权
标题翻译：一次性具有2位状态的RDMA
公开(公告)号：US20040034725A1
公开(公告)日：2004-02-19
申请号：US10642023
申请日：2003-08-14
发明人： Uri Elzur
IPC分类号： G06F013/28
CPC分类号： G06F13/28 , H04L67/1097
摘要： A system and method for managing memory resources in a system that allows remote direct access of memory. An aspect of the invention provides for automatically un-binding bound direct-access memory resources based on information received in messages from a remote source. The information may, for example, include a last-segment indicator to indicate that the message segment is the last expected message segment for a message. Another aspect of the invention provides for memory management of directly-accessible sections of memory by assigning a flag to indicate when the section of memory has special access restrictions, such as a set number of allowable accesses. Yet another aspect of the invention provides for a flag to represent when the access restrictions associated with a particular section of memory have been met.
摘要翻译：一种用于管理允许远程直接访问存储器的系统中的存储器资源的系统和方法。本发明的一个方面提供了基于在来自远程源的消息中接收的信息来自动解除绑定的绑定的直接访问存储器资源。该信息可以例如包括最后一段指示符以指示该消息段是消息的最后期望消息段。本发明的另一方面通过分配一个标志来指示存储器的哪一段具有特殊的访问限制（诸如允许访问的设定数量）来提供存储器直接可访问部分的存储器管理。本发明的另一方面提供了一种标志来表示何时已经满足与特定存储器部分相关联的访问限制。

22. 发明申请

US20040030814A1 Reflective mirror for lithographic exposure and production method 失效
标题翻译：光刻曝光反射镜及制作方法
公开(公告)号：US20040030814A1
公开(公告)日：2004-02-12
申请号：US10632752
申请日：2003-08-01
发明人： Frank-Michael Kamm , Jenspeter Rau
IPC分类号： G06F013/28
CPC分类号： G03F1/24 , B82Y10/00 , B82Y40/00 , G03F7/70958
摘要： The present invention, generally speaking, provides an efficient method of sending a long message from a first compute node to a second compute node across an interconnection network. In the first compute node, a message header field is set to a predetermined value and the message is sent. In the second compute node, the message header is received and processed, and a memory location is read in accordance with the contents of a base address register and an index register. Using Direct Memory Access, the message is then stored in memory at a storage address determined in accordance with the contents of the memory location. Preferably, the storage address is aligned on a memory page boundary.
摘要翻译：一般而言，本发明提供了一种通过互连网络将长消息从第一计算节点发送到第二计算节点的有效方法。在第一计算节点中，将消息报头字段设置为预定值并发送消息。在第二计算节点中，接收并处理消息报头，并且根据基地址寄存器和索引寄存器的内容来读取存储器位置。使用直接存储器访问，然后将消息以根据存储器位置的内容确定的存储地址存储在存储器中。优选地，存储地址在存储器页边界上对齐。

23. 发明申请

US20040028053A1 Direct memory access circuit with ATM support 审中-公开
标题翻译：具有ATM支持的直接存储器存取电路
公开(公告)号：US20040028053A1
公开(公告)日：2004-02-12
申请号：US10454750
申请日：2003-06-03
申请人： Catena Networks, Inc.
发明人： Ian Mes
IPC分类号： G06F013/28 , H04L012/56
CPC分类号： H04L12/5601 , G06F13/30 , H04L2012/5652
摘要： A direct memory access (DMA) circuit reduces the number of processor cycles involved in transmitting and receiving asynchronous transfer mode (ATM) cells. The circuit includes a read sequencer, a write sequencer, an ATM control block, a processor interface block, and a DMA arbitration and control block. The DMA arbitration and control block arbitrates between data transmissions on various subchannels. The ATM control block provides ATM functionality to the DMA circuit. The circuit may also respond to a trigger signal and may generate an interrupt signal. In this manner, the processing involved for DMA of ATM cells is improved.
摘要翻译：直接存储器访问（DMA）电路减少了发送和接收异步传输模式（ATM）单元中涉及的处理器周期数。该电路包括读序列器，写定序器，ATM控制块，处理器接口块和DMA仲裁和控制块。 DMA仲裁和控制块在各个子信道上的数据传输之间进行仲裁。 ATM控制块向DMA电路提供ATM功能。电路还可以响应触发信号并且可以产生中断信号。以这种方式，提高了对ATM信元的DMA的处理。

24. 发明申请

US20040024833A1 Key reuse for RDMA virtual address space 有权
标题翻译： RDMA虚拟地址空间的密钥重用
公开(公告)号：US20040024833A1
公开(公告)日：2004-02-05
申请号：US10210725
申请日：2002-07-31
发明人： Ajoy C. Siddabathuni
IPC分类号： G06F015/167 , G06F013/28
CPC分类号： G06F13/28
摘要： A system and method for reusing an R_Key associated with InfiniBand virtual address space mapped to local, host, storage. An R_Key is initially assigned by an HCA (Host Channel Adapter) when a host registers a set of local storage buffers. The HCA maps the local buffers to virtual address space and returns the R_Key. When the host augments the mapped local storage by identifying additional buffers, the HCA maps the larger storage area to virtual address space and returns the same R_Key. When the host removes local storage from the mapping scheme, the HCA returns a smaller virtual address space associated with the same R_Key.
摘要翻译：用于重新使用映射到本地，主机，存储的InfiniBand虚拟地址空间的R_Key的系统和方法。当主机注册一组本地存储缓冲区时，R_Key最初由HCA（主机通道适配器）分配。 HCA将本地缓冲区映射到虚拟地址空间并返回R_Key。当主机通过识别附加缓冲区来增强映射的本地存储时，HCA将较大的存储区域映射到虚拟地址空间并返回相同的R_Key。当主机从映射方案中删除本地存储时，HCA返回与相同R_Key相关联的更小的虚拟地址空间。

25. 发明申请

US20040019711A1 Method, system, and program for handling input/output commands 有权
标题翻译：用于处理输入/输出命令的方法，系统和程序
公开(公告)号：US20040019711A1
公开(公告)日：2004-01-29
申请号：US10205663
申请日：2002-07-24
申请人： Intel Corporation
发明人： Sailesh Bissessur , Richard P. Mackey , Mark A. Schmisseur , David R. Smith
IPC分类号： G06F013/28
CPC分类号： G06F13/28
摘要： Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. Te device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
摘要翻译：提供了一种用于处理输入/输出（I / O）请求的方法，系统和程序。总线使得能够与发起者，目标设备和设备控制器进行通信，其中设备控制器访问目标设备以执行指向目标设备的I / O命令。接收到I / O请求命令以访问目标设备。启动器被配置为将总线上的至少一个数据请求发送到设备控制器的预定义地址窗口中的一个存储器地址。 Te设备控制器被允许从总线上的启动器向预定义地址窗口中的存储器地址提出数据请求，以针对目标设备执行数据请求。

26. 发明申请

US20040006667A1 Apparatus and method for implementing adjacent, non-unit stride memory access patterns utilizing SIMD instructions 审中-公开
标题翻译：用于使用SIMD指令实现相邻的非单位步进存储器访问模式的装置和方法
公开(公告)号：US20040006667A1
公开(公告)日：2004-01-08
申请号：US10177556
申请日：2002-06-21
发明人： Aart J.C. Bik , Milind Girkar
IPC分类号： G06F012/00 , G06F012/14 , G06F012/16 , G06F013/00 , G06F013/28 , G06F009/45
CPC分类号： G06F8/452
摘要： An apparatus and method for implementing adjacent, single non-unit stride memory access patterns are described. In one embodiment, the method includes compiler analysis of a source program to detect vectorizable loops having serial code statements that collectively perform adjacent, non-unit stride memory access. Once a vectorizable loop containing code statements that collectively perform adjacent, non-unit stride memory access in detected, the compiler vectorizes the serial code statements of the detected loop to perform the adjacent, non-unit stride memory access utilizing SIMD instructions. As such, the compiler repeats the analysis and vectorization for each vectorizable loop within the source program code.
摘要翻译：描述了用于实现相邻的单个非单步步进存储器访问模式的装置和方法。在一个实施例中，该方法包括源程序的编译器分析以检测具有串行代码语句的可矢量化的循环，这些循环代码语句共同执行相邻的非单位步进存储器访问。一旦包含代码语句的可矢量化循环，它们共同执行检测到的相邻的非单位步进存储器访问，则编译器对检测到的循环的序列代码语句进行矢量化，以使用SIMD指令来执行相邻的非单位步进存储器访问。因此，编译器重复对源程序代码内的每个可矢量化循环的分析和向量化。

27. 发明申请

US20030229698A1 Data allocation method, program and computer 审中-公开
标题翻译：数据分配方法，程序和计算机
公开(公告)号：US20030229698A1
公开(公告)日：2003-12-11
申请号：US10230101
申请日：2002-08-29
发明人： Ryoji Furuhashi , Yasunori Kaneda , Toru Nojiri
IPC分类号： G06F015/173 , G06F012/00 , G06F017/30 , G06F012/16 , G06F007/00 , G06F013/00 , G06F013/28
CPC分类号： G06F3/0601 , G06F2003/0697 , H04L29/06 , H04L67/10
摘要： An information processing system has a computer, a plurality of memory devices for storing data used by a program of the computer and an allocation unit for allocating the data to a predetermined storage area for data storage. The allocation unit determines a position of a storage area for allocation on the basis of characteristic information of a memory device and volume requirement information indicative of the kind or utilization purpose of the data.
摘要翻译：信息处理系统具有计算机，用于存储由计算机的程序使用的数据的多个存储器装置和用于将数据分配给用于数据存储的预定存储区域的分配单元。分配单元基于存储装置的特征信息和指示数据的种类或使用目的的体积要求信息来确定用于分配的存储区域的位置。

28. 发明申请

US20030212839A1 System including real-time data communication features 失效
标题翻译：系统包括实时数据通信功能
公开(公告)号：US20030212839A1
公开(公告)日：2003-11-13
申请号：US10145244
申请日：2002-05-13
申请人： Intel Corporation
发明人： Prashant Sethi , Carl L. First , Krishnan Rajamani
IPC分类号： G06F013/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： A system includes a direct memory access (DMA) engine to move data on a real time basis and a communication front-end to transmit and receive the data. In another embodiment, the system may also include a medium access control (MAC) to control transmission and reception of the data and that may be partitioned or divided according to response times to carry out selected functions.
摘要翻译：系统包括直接存储器访问（DMA）引擎，以实时地移动数据和通信前端来发送和接收数据。在另一个实施例中，系统还可以包括用于控制数据的传输和接收的介质访问控制（MAC），并且可以根据响应时间进行分区或划分以执行所选择的功能。

29. 发明申请

US20030182493A1 Method of self-refresh in large memory arrays 失效
标题翻译：大型存储器阵列中的自刷新方法
公开(公告)号：US20030182493A1
公开(公告)日：2003-09-25
申请号：US10104544
申请日：2002-03-22
发明人： David W. Frame , Edward Butler
IPC分类号： G06F013/28 , G06F013/00 , G06F012/16 , G06F012/14 , G06F012/00
CPC分类号： G11C11/406
摘要： A method of self-refresh in a memory array includes initializing a programmable refresh counter of a memory module to an offset value from at least another memory module in the memory array. A data line carrying a system-wide self-refresh indicator signal is interrogated to determine whether any memory module is in a self-refresh mode. The self-refresh mode for the memory module is entered if the programmable refresh counter indicates that a self-refresh cycle is due, and it is determined that no other memory modules are in the self-refresh mode.
摘要翻译：存储器阵列中的自刷新方法包括将存储器模块的可编程刷新计数器初始化为来自存储器阵列中的至少另一个存储器模块的偏移值。询问携带全系统自刷新指示符信号的数据线，以确定任何存储器模块是否处于自刷新模式。如果可编程刷新计数器指示自刷新周期到期，并且确定没有其他存储器模块处于自刷新模式，则输入存储器模块的自刷新模式。

30. 发明申请

US20030145139A1 DMA transfer method 失效
标题翻译： DMA传输方式
公开(公告)号：US20030145139A1
公开(公告)日：2003-07-31
申请号：US10382391
申请日：2003-03-06
发明人： Yasuhiro Kubo
IPC分类号： G06F013/28
CPC分类号： G06F13/28
摘要： A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means for executing a first DMA transfer from said first stream storing means to said main storage unit; first DMA transfer controlling means for controlling said first DMA transfer executing means on the basis of an amount of data which are stored in said first stream storing means or a free capacity; a processing unit which produces a second stream from the first stream that is read out from said main storage unit, and which writes the second stream into said main storage unit; second stream storing means for storing the second stream of said main storage unit; second DMA transfer executing means for executing a second DMA transfer from said main storage unit to said second stream storing means; and second DMA transfer controlling means for controlling said second DMA transfer executing means on the basis of an amount of data which are stored in said second stream storing means or a free capacity.
摘要翻译： DMA传输设备具有用于接收编码的第一流的流输入装置; 第一流存储装置，用于存储第一流; 存储所述第一流存储装置的流的主存储单元; 第一DMA传送执行装置，用于执行从所述第一流存储装置到所述主存储单元的第一DMA传送; 第一DMA传送控制装置，用于根据存储在所述第一流存储装置中的数据量或空闲容量来控制所述第一DMA传送执行装置; 处理单元，其从所述第一流产生从所述主存储单元读出的第二流，并将所述第二流写入所述主存储单元; 第二流存储装置，用于存储所述主存储单元的第二流; 第二DMA传送执行装置，用于执行从所述主存储单元到所述第二流存储装置的第二DMA传送; 以及第二DMA传送控制装置，用于根据存储在所述第二流存储装置中的数据量或空闲容量来控制所述第二DMA传送执行装置。

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