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21. 发明授权

US07923828B2 Structure and method of making interconnect element, and multilayer wiring board including the interconnect element 有权
标题翻译：制造互连元件的结构和方法，以及包括互连元件的多层布线板
公开(公告)号：US07923828B2
公开(公告)日：2011-04-12
申请号：US11239744
申请日：2005-09-30
申请人： Kimitaka Endo , Norihito Masuda , Tomokazu Shimada
发明人： Kimitaka Endo , Norihito Masuda , Tomokazu Shimada
IPC分类号： H01R13/60
CPC分类号： H05K3/4617 , H01L21/4857 , H01L23/49822 , H01L23/5383 , H01L2924/0002 , H05K3/064 , H05K3/205 , H05K3/423 , H05K3/4647 , H05K2203/0384 , H05K2203/0542 , H05K2203/0733 , Y10S438/931 , Y10T29/49124 , H01L2924/00
摘要： An interconnect element is provided which includes a dielectric element having a first major surface, a second major surface remote from the first major surface, and a plurality of recesses extending inwardly from the first major surface. A plurality of metal traces are embedded in the plurality of recesses, the metal traces having outer surfaces substantially co-planar with the first major surface and inner surfaces remote from the outer surfaces. A plurality of posts extend from the inner surfaces of the plurality of metal traces through the dielectric element, the plurality of posts having tops exposed at the second major surface. A multilayer wiring board including a plurality of such interconnect elements is also provided, as well as various methods for making such interconnect elements and multilayer wiring boards.
摘要翻译：提供互连元件，其包括具有第一主表面的电介质元件，远离第一主表面的第二主表面和从第一主表面向内延伸的多个凹槽。多个金属迹线嵌入在多个凹槽中，金属迹线具有与第一主表面和远离外表面的内表面基本上共面的外表面。多个柱从多个金属迹线的内表面延伸通过介电元件，多个柱具有在第二主表面处露出的顶部。还提供了包括多个这种互连元件的多层布线板，以及用于制造这种互连元件和多层布线板的各种方法。

22. 发明授权

US07888256B2 Process for forming an interface between silicon carbide and silicon oxide with low density of states 有权
标题翻译：用于在低密度状态下形成碳化硅和氧化硅之间的界面的方法
公开(公告)号：US07888256B2
公开(公告)日：2011-02-15
申请号：US12069198
申请日：2008-02-08
申请人： Giovanni Abagnale , Dario Salinas , Sebastiano Ravesi
发明人： Giovanni Abagnale , Dario Salinas , Sebastiano Ravesi
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： H01L21/31662 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/02378 , H01L21/02447 , H01L21/02529 , H01L21/02576 , H01L21/02634 , H01L29/66068 , Y10S438/931
摘要： An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.
摘要翻译：公开了一种在设计成导通电流的结构的碳化硅（SiC）层和氧化硅（SiO 2）层之间形成界面的方法的实施例。具有第一掺杂水平的第一外延层在衬底上同时生长。在外延生长之前，在第一外延层上生长具有高于第一掺杂水平的第二掺杂水平的第二外延层。最后，第二外延层被氧化以完全去除。由此，形成高质量的氧化硅层，第二外延层与氧化硅之间的界面具有低陷阱密度。

23. 发明授权

US07875545B2 Silicon-rich nickel-silicide ohmic contacts for SiC semiconductor devices 有权
标题翻译：用于SiC半导体器件的富含硅的硅化镍欧姆接触
公开(公告)号：US07875545B2
公开(公告)日：2011-01-25
申请号：US12020731
申请日：2008-01-28
申请人： Allan Ward, III , Jason Patrick Henning , Helmut Hagleitner , Keith Dennis Wieber
发明人： Allan Ward, III , Jason Patrick Henning , Helmut Hagleitner , Keith Dennis Wieber
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/1608 , H01L21/0455 , H01L21/0485 , H01L29/45 , Y10S438/931
摘要： A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.
摘要翻译：公开了一种制造欧姆接触和产生的欧姆接触结构的方法。该方法包括以下步骤：在碳化硅表面上形成沉积的镍和硅的膜，其温度低于任何一种元素将与碳化硅反应并以相应的比例使沉积膜中硅的原子比分数大于将镍和硅的原子分数加热至镍 - 硅化合物形成的温度，其中硅的原子分数大于镍的原子分数，但低于任一元素将与硅反应的温度碳化物。该方法还可以包括将镍硅化合物退火至高于沉积膜的加热温度的温度，并且在不存在游离碳的相图的区域内。

24. 发明授权

US07799600B2 Doped diamond LED devices and associated methods 有权
标题翻译：掺杂的钻石LED器件及相关方法
公开(公告)号：US07799600B2
公开(公告)日：2010-09-21
申请号：US12127453
申请日：2008-05-27
申请人： Chien-Min Sung
发明人： Chien-Min Sung
IPC分类号： H01L21/00
CPC分类号： H01L33/32 , H01L33/0025 , H01L33/34 , H01L33/641 , Y10S438/931
摘要： LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.
摘要翻译：提供了用于制造这种装置的LED装置和方法。一种这样的方法可以包括在基本上单晶Si晶片上外延地形成基本上单晶SiC层，在SiC层上外延地形成基本单晶金刚石层，掺杂金刚石层以形成导电金刚石层，将Si晶片除去暴露与导电金刚石层相对的SiC层，在SiC层上外延形成多个半导体层，使得至少一个半导体层接触SiC层，并将n型电极耦合到半导体中的至少一个使得多个半导体层功能地位于导电金刚石层和n型电极之间。

25. 发明申请

US20100159653A1 METHOD FOR MANUFACTURING ION IMPLANTATION MASK, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造离子植入掩模的方法和用于制造碳化硅半导体器件的方法
公开(公告)号：US20100159653A1
公开(公告)日：2010-06-24
申请号：US12716916
申请日：2010-03-03
申请人： Ken-ichi NONAKA , Hideki HASHIMOTO , Seiichi YOKOYAMA , Hiroaki IWAKURO , Koichi NISHIKAWA , Masaaki SHIMIZU , Yusuke FUKUDA
发明人： Ken-ichi NONAKA , Hideki HASHIMOTO , Seiichi YOKOYAMA , Hiroaki IWAKURO , Koichi NISHIKAWA , Masaaki SHIMIZU , Yusuke FUKUDA
IPC分类号： H01L21/336 , H01L21/314
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
摘要翻译：公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。所获得的离子注入掩模用于形成更深的选择性导电区域。

26. 发明申请

US20100151671A1 NOVEL AIR GAP INTEGRATION SCHEME 有权
标题翻译：新的空气隙整合方案
公开(公告)号：US20100151671A1
公开(公告)日：2010-06-17
申请号：US12714865
申请日：2010-03-01
申请人： Alexandros T. Demos , Li-Qun Xia , Bok Hoen Kim , Derek R. Witty , Hichem M'Saad
发明人： Alexandros T. Demos , Li-Qun Xia , Bok Hoen Kim , Derek R. Witty , Hichem M'Saad
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , C23C16/401 , C23C16/56 , H01L21/02115 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02351 , H01L21/02362 , H01L21/3146 , H01L21/31633 , H01L21/31695 , H01L21/76811 , H01L21/76835 , H01L2221/1047 , Y10S438/931
摘要： Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.
摘要翻译：提供了用于形成包括气隙的结构的方法。在一个实施例中，提供了一种用于形成镶嵌结构的方法，包括通过包括使有机硅化合物和致孔剂提供前体反应的方法沉积多孔低介电常数层，沉积含致孔剂的材料，以及除去至少一部分含致孔剂的材料，通过使造孔剂提供前体反应，在有机层中形成特征定义和多孔低介电常数层，在多孔低介电常数层上沉积有机层，用导电材料填充特征定义在有机层上沉积掩模层和设置在特征定义中的导电材料，在掩模层中形成孔以暴露有机层，通过孔去除部分或全部有机层，并形成相邻的气隙导电材料。

27. 发明授权

US07727340B2 Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects 有权
标题翻译：在二氧化硅 - 碳化硅界面处纳入氮以钝化界面缺陷
公开(公告)号：US07727340B2
公开(公告)日：2010-06-01
申请号：US11811396
申请日：2007-06-08
申请人： Gilyong Y. Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano De Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
发明人： Gilyong Y. Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano De Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
IPC分类号： H01L21/3105
CPC分类号： H01L21/3145 , H01L21/0214 , H01L21/02164 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/045 , H01L21/049 , H01L21/31658 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/66068 , Y10S438/931
摘要： In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.
摘要翻译：一方面，本发明提供一种制造碳化硅半导体器件的方法。在碳化硅衬底上形成二氧化硅层，并且在二氧化硅/碳化硅界面上并入氮。在一个实施方案中，通过在一氧化氮或一氧化二氮中对半导体器件进行退火来引入氮。在另一个实施方案中，通过用氨将半导体器件退火而并入氮气。

28. 发明授权

US07709862B2 Ion implantation mask and method for manufacturing same, silicon carbide semiconductor device using ion implantation mask, and method for manufacturing same 失效
标题翻译：离子注入掩模及其制造方法，使用离子注入掩模的碳化硅半导体器件及其制造方法
公开(公告)号：US07709862B2
公开(公告)日：2010-05-04
申请号：US11496627
申请日：2006-08-01
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
IPC分类号： H01L29/76
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
摘要翻译：公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。所获得的离子注入掩模用于形成更深的选择性导电区域。

29. 发明授权

US07705362B2 Silicon carbide devices with hybrid well regions 有权
标题翻译：具有混合井区的碳化硅器件
公开(公告)号：US07705362B2
公开(公告)日：2010-04-27
申请号：US11513473
申请日：2006-08-31
申请人： Mrinal Kanti Das , Sei-Hyung Ryu
发明人： Mrinal Kanti Das , Sei-Hyung Ryu
IPC分类号： H01L31/0312
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7395 , Y10S438/931
摘要： MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.
摘要翻译：提供了MOS通道器件和制造具有混合通道的器件的方法。示例性器件包括垂直功率MOSFET，其包括碳化硅的混合阱区域以及制造这种器件的方法。混合阱区可以包括在p型碳化硅外延层中注入的p型碳化硅阱部分，注入的p型碳化硅接触部分，其与注入的p型碳化硅阱部分接触并延伸到表面的p型外延层和/或外延p型碳化硅部分的至少一部分，所述外延p型碳化硅阱部分的至少一部分对应于所述MOSFET的p型沟道区。

30. 发明授权

US07691694B2 Silicon carbide semiconductor device having junction field effect transistor and method for manufacturing the same 有权
标题翻译：具有结场效应晶体管的碳化硅半导体器件及其制造方法
公开(公告)号：US07691694B2
公开(公告)日：2010-04-06
申请号：US11785276
申请日：2007-04-17
申请人： Rajesh Kumar , Andrei Mihaila , Florin Udrea
发明人： Rajesh Kumar , Andrei Mihaila , Florin Udrea
IPC分类号： H01L21/337
CPC分类号： H01L29/1608 , H01L29/66068 , H01L29/8083 , Y10S438/931
摘要： A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.
摘要翻译：碳化硅半导体器件包括衬底和结场效应晶体管。晶体管包括：设置在基板上的第一半导体层; 设置在所述第一半导体层的表面上的第一栅极层; 与所述基板上的所述第一栅极层相邻的第一沟道层; 电连接到第一沟道层的第一源极层; 与所述第一沟道层相邻以夹住所述第一沟道层的第二栅极层; 与所述第二栅极层相邻以夹住所述第二栅极层的第二沟道层; 与所述第二沟道层相邻以夹住所述第二沟道层的第三栅极层; 以及电连接到第二沟道层的第二源极层。

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