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21. 发明授权

US07386076B2 Space time encoded wireless communication system with multipath resolution receivers 有权
标题翻译：具有多路分辨率接收机的时空编码无线通信系统
公开(公告)号：US07386076B2
公开(公告)日：2008-06-10
申请号：US10107275
申请日：2002-03-26
申请人： Eko N. Onggosanusi , Anand G Dabak
发明人： Eko N. Onggosanusi , Anand G Dabak
IPC分类号： H04B7/10 , H04L1/02
CPC分类号： H04L25/03114 , H04L1/0618 , H04L2025/03605
摘要： A wireless receiver (301) for receiving multiple space time encoded signals from a plurality of transmit antenna sets (TAT1 through TAT2, and TAT3 through TAT4), wherein the multiple space time encoded signals comprise a set of symbols and wherein each transmit antenna set is coupled to a corresponding encoder (221, 222) at a single transmitter (121). The receiver comprises a plurality of receive antennas (RAT1 through RATQ) and collection circuitry (32), coupled to the plurality of receive antennas, for collecting a plurality of signal samples for a plurality of successive time instances and from each of the plurality of receive antennas. The collected samples comprise samples of multipaths of the space time encoded signals. The receiver also comprises circuitry (34, 36), coupled to the plurality of receive antennas, for determining a linear time invariant multiple-input multiple-output matrix in response to pilot values in the received multiple space time encoded signals. Finally, the receiver comprise circuitry (40, 421, 441) for estimating at least selected ones of the symbols in response to the signal samples and the linear time invariant multiple-input multiple-output matrix.
摘要翻译：用于从多个发射天线组（TAT 1至TAT 2 2）接收多个空时编码信号的无线接收机（30 1）和其中多个时空编码信号包括一组符号，并且其中每个发射天线组耦合到相应的编码器（22），其中， 1，12 2，2）在单个发射器（12 1 1）处。接收机包括耦合到多个接收天线的多个接收天线（RAT 1至RAT 1）和收集电路（32），用于收集多个信号用于多个连续时间实例和来自多个接收天线中的每一个的样本。收集的样本包括空时编码信号的多路径样本。接收机还包括耦合到多个接收天线的电路（34,36），用于响应于所接收的多个时空编码信号中的导频值来确定线性时间不变的多输入多输出矩阵。最后，接收机包括用于响应于信号样本和线性时间不变倍数来估计符号中的至少一个选择符号的电路（40,42，...，44）输入多输出矩阵。

22. 发明授权

US07177378B2 Minimization of error contributions in a DMT system 有权
标题翻译：最小化DMT系统中的错误贡献
公开(公告)号：US07177378B2
公开(公告)日：2007-02-13
申请号：US10101505
申请日：2002-03-20
申请人： Robert Baldemair , P{dot over (a)}l Frenger
发明人： Robert Baldemair , P{dot over (a)}l Frenger
IPC分类号： H03D1/06
CPC分类号： H04L25/03114 , H04L27/2647 , H04L2025/03414 , H04L2025/03471 , H04L2025/03509 , H04L2025/03592
摘要： Error contributions in a DMT system where a received DMT-signal is effected by intersymbol interference, intercarrier interference and additive noise are minimized. Intersymbol interference average power, intercarrier interference average power, and additive noise average power are calculated. A cost function is determined by adding the intersymbol interference average power, the intercarrier interference average power, and the additive noise average power. A constraint is introduced which avoids a trivial solution where a time domain equalizer (TEQ) vector is equal to zero. The cost function is minimized by optimizing the TEQ vector.
摘要翻译： DMT系统中的错误贡献是通过码间干扰，载波间干扰和附加噪声来实现接收的DMT信号。计算符号间干扰平均功率，载波间干扰平均功率和加性噪声平均功率。通过加入符号间干扰平均功率，载波间干扰平均功率和加性噪声平均功率来确定成本函数。引入了约束，其避免了时域均衡器（TEQ）向量等于零的微不足道的解决方案。通过优化TEQ向量来最小化成本函数。

23. 发明授权

US07042935B2 Equalizer and equalization method 失效
标题翻译：均衡器和均衡方法
公开(公告)号：US07042935B2
公开(公告)日：2006-05-09
申请号：US10011273
申请日：2001-12-11
申请人： Nobuaki Kawahara , Masashi Naito
发明人： Nobuaki Kawahara , Masashi Naito
IPC分类号： H03H7/30
CPC分类号： H04L25/03114 , H04L7/04 , H04L2025/0342 , H04L2025/0377
摘要： An equalizer and an equalization method capable of suppressing distortion specific to radio unit and reducing both the oversampling number and the amount of calculations without causing characteristic deterioration. The equalizer, which equalizes a received signal with periodically inserted known pilot symbols, includes a synchronization processing section that detects symbol synchronization points using pilot symbols included in the received signal, a plurality of equalization factor calculation sections which use the symbol synchronization points and points shifted in time before and after the symbol synchronization point as symbol synchronization point candidates, and calculate equalization factors for the respective symbol synchronization point candidates, and an optimization/equalization processing section which selects an optimal symbol synchronization point and corresponding optimal equalization factor from among a plurality of symbol synchronization point candidates and corresponding equalization factors, and equalizes the received signal using the optimal equalization factor.
摘要翻译：一种均衡器和均衡方法，其能够抑制无线电单元特有的失真并减少过采样数量和计算量而不引起特性劣化。使用周期性插入的已知导频符号来均衡接收信号的均衡器包括使用包括在接收信号中的导频符号来检测符号同步点的同步处理部分，使用符号同步点和偏移点的多个均衡因子计算部分在符号同步点之前和之后的时间作为符号同步点候选，并计算各个符号同步点候选的均衡因子，以及优化/均衡处理部，其从多个中选择最佳符号同步点和对应的最优均衡因子的符号同步点候选和相应的均衡因子，并且使用最优均衡因子来均衡接收信号。

24. 发明授权

US4303896A Wide range data cable equalizer 失效
标题翻译：宽范围数据线均衡器
公开(公告)号：US4303896A
公开(公告)日：1981-12-01
申请号：US151858
申请日：1980-05-21
申请人： Chet J. Slabinski
发明人： Chet J. Slabinski
IPC分类号： H03H7/01 , H04B3/04 , H04B3/40 , H04L25/03 , H03H7/03 , H03H7/32
CPC分类号： H04B3/40 , H04L25/03114
摘要： An equalizer circuit arrangement is provided for use without readjustment for a wide range of transmission line lengths. The circuit (10) is comprised of a resistor (20) and a capacitor (22) which introduce an additional time constant delay into the transmission system in order to reduce the percentage change of the transmission line response time for the shortest line used as compared to the longest line employed. This reduction permits one equalizer to be designed and used for the complete range of transmission line lengths involved.
摘要翻译：提供了一种均衡器电路装置，用于不需要在宽范围的传输线路长度内进行调整。电路（10）由电阻器（20）和电容器（22）构成，电容器（22）对传输系统引入额外的时间常数延迟，以便减少所用最短线路的传输线响应时间的百分比变化到最长的线。这种减少允许一个均衡器被设计并用于所涉及的传输线路长度的完整范围。

25. 发明授权

US4160157A Signal transmission circuit with improved digital signal recovery 失效
标题翻译：具有改进的数字信号恢复的信号传输电路
公开(公告)号：US4160157A
公开(公告)日：1979-07-03
申请号：US752228
申请日：1976-12-20
申请人： John C. Freeborn
发明人： John C. Freeborn
IPC分类号： H04B10/152 , H04L25/03 , G02B5/14
CPC分类号： H04L25/03114 , H04B10/5057
摘要： A feedback circuit and method are disclosed for restoring high frequency digital signals degraded by signal transmitting means whose upper frequency limit is below that required for accurate signal transmission. The restored digital output signal is supplied by a digitizing circuit which produces a signal having first and second values in response to input signal amplitudes respectively less than and greater than a digitizing threshold. The input signal to the digitizing circuit comprises a combination of the degraded signal, and a feedback signal generated by passing the output signal through a feedback circuit whose response to high frequency signals is substantially identical to that of the signal transmitting means.

26. 发明授权

US2769861A Reduction of interference in pulse reception 失效
标题翻译：减少脉冲接收干扰
公开(公告)号：US2769861A
公开(公告)日：1956-11-06
申请号：US38748553
申请日：1953-10-21
申请人： BELL TELEPHONE LABOR INC
发明人： BLACK HAROLD S
IPC分类号： H04L25/03
CPC分类号： H04L25/03114

27. 发明授权

US2425063A Telegraphic keying bias adjuster 失效
标题翻译：电报键控偏差调节器
公开(公告)号：US2425063A
公开(公告)日：1947-08-05
申请号：US57728845
申请日：1945-02-10
申请人： RCA CORP
发明人： ALFRED KAHN , HARRIS CUTHBERT N
IPC分类号： H04L25/03
CPC分类号： H04L25/03114

28. 发明公开

US20230216713A1 DRIVING ADJUSTMENT CIRCUIT AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20230216713A1
公开(公告)日：2023-07-06
申请号：US17720492
申请日：2022-04-14
申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.
发明人： Yinchuan GU
IPC分类号： H04L25/03 , H03K19/20 , H03K3/037 , G11C7/10
CPC分类号： H04L25/03114 , H03K19/20 , H03K3/037 , G11C7/10
摘要： A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

29. 发明申请

US20180278441A1 MULTIPATH FILTERS 审中-公开
公开(公告)号：US20180278441A1
公开(公告)日：2018-09-27
申请号：US15902190
申请日：2018-02-22
申请人： SKYWORKS SOLUTIONS, INC.
发明人： Alexander John Heaslip Ross , John William Mitchell Rogers
IPC分类号： H04L25/03 , H04B1/16
CPC分类号： H04L25/03828 , H03H19/002 , H04B1/16 , H04L25/03114
摘要： Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

30. 发明申请

US20170279428A1 SYSTEM AND METHOD FOR SETTING ANALOG FRONT END DC GAIN 审中-公开
公开(公告)号：US20170279428A1
公开(公告)日：2017-09-28
申请号：US15621979
申请日：2017-06-13
申请人： Samsung Display Co., Ltd.
发明人： Gaurav Malhotra , Amir Amirkhany
IPC分类号： H03G3/30 , H04B1/16 , H04L25/03
CPC分类号： H03G3/3036 , H03H2021/0065 , H04B1/16 , H04L25/03057 , H04L25/03114 , H04L25/03885 , H04L2025/03636
摘要： A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.

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