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    • 21. 发明申请
    • LOW VOLTAGE ISOLATION SWITCH, IN PARTICULAR FOR A TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS
    • 低电压隔离开关,特别适用于超声波应用的传输通道
    • US20120313689A1
    • 2012-12-13
    • US13536818
    • 2012-06-28
    • Valeria BottarelGiulio RicottiSilvia Marabelli
    • Valeria BottarelGiulio RicottiSilvia Marabelli
    • H03K17/687
    • H03K17/693B06B1/0215H03K17/06H03K17/08122H03K17/08142H03K17/6872H03K17/74
    • A low voltage isolation circuit is coupled between an input terminal for receiving a high voltage signal and an output terminal for transmitting the high voltage signal to a load. The isolation circuit includes a driving block; having a first driving transistor coupled between a first voltage reference and an intermediate node and a second driving transistor coupled between the intermediate node and a second voltage reference; an isolation block connected between the input and output terminals and, through a protection block to the intermediate node. The protection block includes first and second protection transistors (MD1, coupled in anti-series to each other and having control terminals receiving complementary protection driving signals. The isolation block includes a voltage limiter block, a diode block and a control transistor connected across the diode block between the input and output terminals and having a control terminal connected to the intermediate node through the protection block.
    • 低电压隔离电路耦合在用于接收高电压信号的输入端子和用于将高电压信号传输到负载的输出端子之间。 隔离电路包括驱动块; 具有耦合在第一参考电压和中间节点之间的第一驱动晶体管和耦合在中间节点和第二电压基准之间的第二驱动晶体管; 连接在输入和输出端之间的隔离块,并通过保护块连接到中间节点。 保护块包括第一和第二保护晶体管(MD1,彼此反串联并且具有接收互补保护驱动信号的控制端子),隔离块包括一个连接在二极管上的电压限制器块,二极管块和控制晶体管 阻塞在输入和输出端之间,并具有通过保护块连接到中间节点的控制终端。
    • 23. 发明授权
    • Driving circuit with output control circuit and liquid crystal display using same
    • 驱动电路采用输出控制电路和液晶显示器
    • US08018416B2
    • 2011-09-13
    • US11903769
    • 2007-09-24
    • Kai MengXiao-Jing Qi
    • Kai MengXiao-Jing Qi
    • G09G3/36
    • H03K17/284H03K17/06H03K17/6871H03K17/693H03K17/78
    • An exemplary driving circuit (20) includes gate lines (201) that are parallel to each other and that each extend along a first direction; first data lines (202) that are parallel to each other and that each extend along a second direction substantially orthogonal to the first direction; thin film transistors (203) provided in the vicinity of intersections of the gate lines and the data lines; a gate driving circuit (210) connected to the gate lines; a data driving circuit (220) connected to the data lines; an access circuit (230) configured for accessing data signals outputted by the data driving circuit; and an output control circuit (240) configured for receiving the data signals accessed by the access circuit and making the time period in which the data signals are applied to the first data lines in accord with the time period during which the thin film transistors are switched on.
    • 示例性驱动电路(20)包括彼此平行并且沿着第一方向延伸的栅极线(201) 第一数据线(202),其彼此平行并且各自沿着基本上与所述第一方向正交的第二方向延伸; 设置在栅极线和数据线的交叉点附近的薄膜晶体管(203) 连接到所述栅极线的栅极驱动电路(210); 连接到数据线的数据驱动电路(220); 访问电路(230),被配置为访问由数据驱动电路输出的数据信号; 以及输出控制电路(240),其被配置为接收由所述存取电路访问的数据信号,并且根据所述薄膜晶体管被切换的时间周期将所述数据信号施加到所述第一数据线的时间段 上。
    • 25. 发明申请
    • Highly Efficient III-Nitride Power Conversion Circuit
    • 高效III氮化物电源转换电路
    • US20110157949A1
    • 2011-06-30
    • US13043235
    • 2011-03-08
    • Tony Bahramian
    • Tony Bahramian
    • H02M3/155
    • H02M7/537H02M1/08H02M3/1584H02M3/1588H03K17/04H03K17/06H03K2017/6875Y02B70/1466
    • According to an exemplary embodiment, a III-nitride power conversion circuit includes a gate driver having a plurality of cascaded inverters, each of the plurality of cascaded inverters including at least one III-nitride transistor. At least one of the plurality of cascaded inverters has a cutoff switch and a III-nitride depletion mode load where the cutoff switch is configured to disconnect the III-nitride depletion mode load so as to prevent current from flowing from a supply voltage of the at least one of the plurality of cascaded inverters. The cutoff switch of the at least one of the plurality of cascaded inverters can be driven by one of the plurality of cascaded inverters. The III-nitride power conversion circuit can also include an output driver driven by the gate driver where the output driver has a segmented III-nitride transistor. Furthermore, a selector circuit can be configured to selectively disable at least one segment of the segmented III-nitride transistor.
    • 根据示例性实施例,III族氮化物功率转换电路包括具有多个级联的反相器的栅极驱动器,多个级联的反相器中的每一个包括至少一个III族氮化物晶体管。 多个级联逆变器中的至少一个具有截止开关和III族氮化物耗尽模式负载,其中截止开关被配置为断开III族氮化物耗尽模式负载,以便防止电流从at的供应电压流出 多个级联逆变器中的至少一个。 多个级联逆变器中的至少一个的截止开关可以由多个级联的逆变器之一驱动。 III族氮化物功率转换电路还可以包括由栅极驱动器驱动的输出驱动器,其中输出驱动器具有分段III族氮化物晶体管。 此外,选择器电路可以被配置为选择性地禁用分段III族氮化物晶体管的至少一个段。
    • 26. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07777518B2
    • 2010-08-17
    • US12471720
    • 2009-05-26
    • Yoshiaki ToyodaKenichi IshiiMorio Iwamizu
    • Yoshiaki ToyodaKenichi IshiiMorio Iwamizu
    • H03K17/16H03K19/003
    • H03K17/0828H03K17/06H03K2017/066
    • A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element.
    • 在下拉晶体管的栅极端子和接收栅极信号的阈值电路之间设置缓冲电路作为输入信号。 从外部电池电源向功率半导体元件的输出端施加的电压通过电阻元件供给缓冲电路。 缓冲电路将来自阈值电路的导通信号输出的电平转换成高于下拉晶体管的阈值的电压,使得下拉晶体管可靠地工作以关闭功率半导体元件,即使当电平 的门信号为低电平。 因此,提供了具有功率半导体元件的半导体集成电路器件,该功率半导体元件可以通过下拉半导体元件的可靠操作而被关断。
    • 27. 发明申请
    • DRIVE CIRCUIT FOR POWER ELEMENT
    • 功率元件驱动电路
    • US20100141304A1
    • 2010-06-10
    • US12667306
    • 2007-07-03
    • Yuji Miyazaki
    • Yuji Miyazaki
    • G05F5/00
    • H02M1/08H03K17/06H03K17/567H03K2017/066H03K2217/0045H03K2217/0081
    • A driving circuit (1) for an IGBT (10) comprises an H bridge circuit (80) using first to fourth switching elements (Q1-Q4). A control unit (20) switches the states of the switching elements from a first state in which the first and fourth switching elements (Q1, Q4) are set to be in an on state and the second and third switching elements (Q2, Q3) are set to be in an off state to a second state in which the first and fourth switching elements (Q1, Q4) are set to be in an off state and the second and third switching elements (Q2, Q3) are set to be in an on state when receiving an order to make the IGBT (10) transit from an on state to an off state. With the structure of the driving circuit (1) described above, reverse bias can be applied to the IGBT (10) by use of a single power source (15).
    • IGBT(10)的驱动电路(1)包括使用第一至第四开关元件(Q1-Q4)的H桥电路(80)。 控制单元(20)将开关元件的状态从第一和第四开关元件(Q1,Q4)设定为导通状态的第一状态和第二和第三开关元件(Q2,Q3) 被设定为处于断开状态,第二状态和第二开关元件(Q1,Q4)被设定为截止状态,第二开关元件(Q3,Q2)设定为第二状态 当接收使IGBT(10)从接通状态转换到断开状态的命令时的接通状态。 利用上述驱动电路(1)的结构,可以通过使用单个电源(15)向IGBT(10)施加反向偏压。
    • 29. 发明申请
    • DRIVING CIRCUIT FOR AN EMITTER-SWITCHING CONFIGURATION OF TRANSISTORS
    • 用于发射极开关晶体管配置的驱动电路
    • US20080180158A1
    • 2008-07-31
    • US12022716
    • 2008-01-30
    • Rosario ScolloMassimo Nania
    • Rosario ScolloMassimo Nania
    • H03K17/60
    • H03K17/567H03K17/0406H03K17/06H03K17/662H03K17/6871
    • A driving circuit for an emitter-switching configuration of transistors having first and second control terminals connected to the driving circuit, forms a controlled emitter-switching device having in turn respective collector, source and gate terminals. The driving circuit comprises a driving block coupled between the collector terminal and the source terminal of the controlled emitter-switching device and connected to the first control terminal of the emitter-switching configuration. Further advantageously, the driving block comprises at least one IGBT driving device coupled between the collector terminal and the first control terminal of the emitter-switching configuration and having, in turn, a third control terminal, as well as a driving bipolar transistor, coupled between the collector terminal and the first control terminal of the emitter-switching configuration for controlling a saturation condition of said bipolar transistor of said emitter-switching configuration maintaining a base-collector junction thereof at a voltage next to zero and having, in turn, a fourth control terminal.
    • 用于具有连接到驱动电路的第一和第二控制端子的晶体管的发射极 - 开关配置的驱动电路形成受控的发射极开关器件,其依次具有集电极,源极和栅极端子。 驱动电路包括耦合在受控发射极开关器件的集电极端子和源极端子之间并连接到发射极开关配置的第一控制端子的驱动块。 进一步有利地,驱动块包括耦合在发射极 - 开关配置的集电极端子和第一控制端子之间的至少一个IGBT驱动器件,并且具有连接在第三控制端子之间的第三控制端子以及驱动双极晶体管 集电极端子和发射极开关配置的第一控制端子,用于控制所述发射极 - 开关配置的所述双极晶体管的饱和状态,将其基极集电极结保持在零下的电压,并且又具有第四 控制终端。