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21. 发明授权

US09287409B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09287409B2
公开(公告)日：2016-03-15
申请号：US14540365
申请日：2014-11-13
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Tatsuya Honda
IPC分类号： H01L29/04 , H01L29/786 , H01L29/778 , H01L29/24 , H01L29/267
CPC分类号： H01L29/7869 , H01L29/045 , H01L29/24 , H01L29/267 , H01L29/7782 , H01L29/78609 , H01L29/78696
摘要： One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.
摘要翻译：本发明的一个目的是提供在晶体管的电特性的阈值电压可以为正的沟道形成区域中的包括氧化物半导体的晶体管的结构，即所谓的常关断开关元件，及其制造方法。在第一氧化物半导体层上形成具有比第一氧化物半导体层更大的电子亲和力和更小的能隙的第二氧化物半导体层。此外，形成第三氧化物半导体层以覆盖第二氧化物半导体层的侧表面和顶表面，即，第三氧化物半导体层覆盖第二氧化物半导体层。

22. 发明授权

US09245990B2 Silicon-compatible germanium-based transistor with high-hole-mobility 有权
标题翻译：硅相容锗基晶体管具有高空穴迁移率
公开(公告)号：US09245990B2
公开(公告)日：2016-01-26
申请号：US14556327
申请日：2014-12-01
申请人： Gachon University of Industry-Academic cooperation Foundation , Seoul National University R&DB Foundation
发明人： Seongjae Cho , Byung-Gook Park
IPC分类号： H01L29/778 , H01L29/12
CPC分类号： H01L29/7782 , H01L29/122 , H01L29/2003 , H01L29/7787
摘要： The present invention provides a silicon-compatible germanium-based high-hole-mobility transistor with high-hole-mobility germanium channel comprising a semiconductor material having a valence band offset instead of the conventional gate insulating film, a germanium channel region, and a quantum well formed by heterojunctions of the upper and lower portions of the germanium channel on a silicon substrate. Thus, the present invention enables to gain maximum hole mobility of the germanium channel by using the two-dimensional hole gas gathered into the quantum well for high-speed and low-power operations and device reliability improvement.
摘要翻译：本发明提供一种具有高空穴迁移率锗通道的硅兼容锗基高空位迁移率晶体管，其包括具有价带偏移的半导体材料，而不是传统的栅极绝缘膜，锗沟道区和量子通过硅衬底上的锗通道的上部和下部的异质结形成。因此，本发明能够通过使用聚集到量子阱中的二维空穴气体来获得锗通道的最大空穴迁移率，用于高速和低功率操作以及器件可靠性的提高。

23. 发明申请

US20150349131A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150349131A1
公开(公告)日：2015-12-03
申请号：US14723630
申请日：2015-05-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tomoaki ATSUMI , Yoshiyuki KOBAYASHI , Yutaka SHIONOIRI , Yuto YAKUBO , Shuhei NAGATSUKA , Shunpei YAMAZAKI
IPC分类号： H01L29/786 , H01L27/12 , H01L29/04 , H01L29/24
CPC分类号： H01L29/7869 , G05F3/262 , H01L27/085 , H01L27/0886 , H01L27/1211 , H01L27/1225 , H01L27/124 , H01L29/045 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/24 , H01L29/66439 , H01L29/66795 , H01L29/7782 , H01L29/785 , H01L29/78648 , H01L29/78696
摘要： A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase rate of a drain current of the transistor with a 0.1 V change in drain voltage is preferably higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the transistor. The semiconductor device has a function of generating a voltage based on the resistance of the resistor.
摘要翻译：提供占据小面积的半导体器件。半导体器件包括电阻器。电阻器包括晶体管。当漏极电压高于晶体管的栅极电压和阈值电压之间的差时，漏极电压的0.1V变化的晶体管的漏极电流的增加率优选地高于或等于1％。半导体器件具有基于电阻器的电阻产生电压的功能。

24. 发明授权

US09153594B2 Nonvolatile memory and three-state FETs using cladded quantum dot gate structure 有权
标题翻译：非易失性存储器和采用包层量子点栅极结构的三态FET
公开(公告)号：US09153594B2
公开(公告)日：2015-10-06
申请号：US12077453
申请日：2008-03-20
申请人： Faquir C. Jain
发明人： Faquir C. Jain
IPC分类号： H01L29/06 , H01L27/115 , G11C11/56 , H01L21/28 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/66 , H01L29/778 , G11C11/412
CPC分类号： H01L27/11521 , G11C11/412 , G11C11/56 , H01L21/28273 , H01L21/28282 , H01L27/1104 , H01L29/1054 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7782 , H01L29/7783
摘要： The present invention discloses use of quantum dot gate FETs as a nonvolatile memory element that can be used in flash memory architecture as well as in a nonvolatile random access memory (NVRAM) configuration that does not require refreshing of data as in dynamic random access memories. Another innovation is the design of quantum dot gate nonvolatile memory and 3-state devices using modulation doped field-effect transistors (MODFETs), particularly MOS-gate field effect transistors. The cladded quantum dot gate MODFETs can be designed in Si—SiGe, InGaAs—InP and other material systems. The incorporation of 3-state FET devices in static random access memory (SRAM) cell is described to result in advanced multi-state memory operation. Unlike conventional SRAMs, the 3-state QD-FET based of SRAMs provides 3 and 4-state memory operation due to the utilization of the intermediate states particularly in CMOS configuration. QD-gate FETs, potentially suitable for 8 nm channel lengths, in vertical configuration (VFET) are also described.
摘要翻译：本发明公开了使用量子点栅极FET作为非易失性存储器元件，其可用于闪速存储器结构以及不需要刷新数据的非易失性随机存取存储器（NVRAM）配置，如在动态随机存取存储器中。另一个创新是使用调制掺杂场效应晶体管（MODFET），特别是MOS栅场效应晶体管的量子点栅非易失性存储器和3态器件的设计。包层的量子点栅极MODFET可以在Si-SiGe，InGaAs-InP等材料体系中进行设计。描述了将三态FET器件并入到静态随机存取存储器（SRAM）单元中以导致高级多状态存储器操作。与传统SRAM不同，由于采用了中间状态，因此，基于SRAM的3态QD-FET可以提供3和4态存储器操作，特别是在CMOS配置中。还描述了垂直配置（VFET）中可能适合于8nm沟道长度的QD栅极FET。

25. 发明申请

US20150206961A1 FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED DOUBLE GATES ON BULK SILICON SUBSTRATE, METHODS OF FORMING, AND RELATED DESIGN STRUCTURES 有权
标题翻译：在自制硅基底板上具有自对准双栅的场效应晶体管（FET），形成方法和相关设计结构
公开(公告)号：US20150206961A1
公开(公告)日：2015-07-23
申请号：US14160630
申请日：2014-01-22
申请人： International Business Machines Corporation
发明人： James W. Adkisson , James S. Dunn , Blaine J. Gross , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L29/778 , H01L29/66 , H01L29/423 , H01L29/16 , H01L21/28 , H01L29/165 , H01L29/15 , H01L29/06 , H01L21/02 , G06F17/50 , H01L29/161
CPC分类号： H01L29/808 , G06F17/5045 , G06F17/505 , G06F17/5072 , H01L21/28026 , H01L21/306 , H01L21/8232 , H01L29/0657 , H01L29/161 , H01L29/47 , H01L29/475 , H01L29/66901 , H01L29/66924 , H01L29/7782 , H01L29/8124
摘要： At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.
摘要翻译：在包括衬底，沟道和上栅极层的层堆叠中形成的至少一个隔离沟槽限定沟道层中的沟道。来自隔离沟槽的横向蚀刻可以在衬底和上部栅极层中形成侧向空腔，以基本上同时形成自对准的下部栅极和上部栅极。下栅极切口通道，上栅极比通道窄，并且可以在通道的相对端形成源极和漏极。因此，可以减小源极 - 漏极电容和栅极 - 漏极电容，从而提高所产生的FET的速度。

26. 发明授权

US09087889B2 Semiconductor devices with 2DEG and 2DHG 有权
标题翻译：具有2DEG和2DHG的半导体器件
公开(公告)号：US09087889B2
公开(公告)日：2015-07-21
申请号：US13812725
申请日：2011-06-07
申请人： Akira Nakajima , Sankara Narayanan Ekkanath Madathil
发明人： Akira Nakajima , Sankara Narayanan Ekkanath Madathil
IPC分类号： H01L29/778 , H01L27/095 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/20
CPC分类号： H01L29/7782 , H01L27/095 , H01L29/1029 , H01L29/2003 , H01L29/42316 , H01L29/7786 , H01L29/7787 , H01L29/782 , H01L29/872
摘要： A semiconductor device comprises three semiconductor layers. The semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer. The device comprises a plurality of electrodes: first and second electrodes electrically connected to the 2DHG so that current can flow between them via the 2DHG and a third electrode electrically connected to the 2DEG so that when a positive voltage is applied to the third electrode, with respect to at least one of the other electrodes, the 2DEG and the 2DHG will be at least partially depleted.
摘要翻译：半导体器件包括三个半导体层。半导体层被布置成形成由偏振层分离的2DHG和2DEG。该装置包括多个电极：电连接到2DHG的第一和第二电极，使得电流可以经由2DHG在它们之间流动，第三电极与2DEG电连接，使得当正电压施加到第三电极时，相对于至少一个其它电极，2DEG和2DHG将至少部分耗尽。

27. 发明申请

US20150155376A1 SILICON-COMPATIBLE GERMANIUM-BASED TRANSISTOR WITH HIGH-HOLE-MOBILITY 有权
标题翻译：具有高孔隙度的基于锗的基于锗的晶体管
公开(公告)号：US20150155376A1
公开(公告)日：2015-06-04
申请号：US14556327
申请日：2014-12-01
申请人： Gachon University of Industry-Academic cooperation Foundation , Seoul National University R&DB Foundation
发明人： Seongjae Cho , Byung-Gook Park
IPC分类号： H01L29/778 , H01L29/12
CPC分类号： H01L29/7782 , H01L29/122 , H01L29/2003 , H01L29/7787
摘要： The present invention provides a silicon-compatible germanium-based high-hole-mobility transistor with high-hole-mobility germanium channel comprising a semiconductor material having a valence band offset instead of the conventional gate insulating film, a germanium channel region, and a quantum well formed by heterojunctions of the upper and lower portions of the germanium channel on a silicon substrate. Thus, the present invention enables to gain maximum hole mobility of the germanium channel by using the two-dimensional hole gas gathered into the quantum well for high-speed and low-power operations and device reliability improvement.
摘要翻译：本发明提供一种具有高空穴迁移率锗通道的硅兼容锗基高空位迁移率晶体管，其包括具有价带偏移的半导体材料，而不是传统的栅极绝缘膜，锗沟道区和量子通过硅衬底上的锗通道的上部和下部的异质结形成。因此，本发明能够通过使用聚集到量子阱中的二维空穴气体来获得锗通道的最大空穴迁移率，用于高速和低功率操作以及器件可靠性的提高。

28. 发明授权

US09000488B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09000488B2
公开(公告)日：2015-04-07
申请号：US13946602
申请日：2013-07-19
申请人： Fujitsu Limited
发明人： Akira Endoh
IPC分类号： H01L29/778 , H01L29/66 , H01L29/423 , H01L29/205
CPC分类号： H01L29/778 , H01L29/205 , H01L29/42316 , H01L29/66462 , H01L29/7782 , H01L29/7784
摘要： A semiconductor device includes: an electron transit layer formed with a semiconductor material, the electron transit layer being formed on a semiconductor substrate; an n-type semiconductor layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the n-type semiconductor layer being formed on the electron transit layer; a δ doping area having an n-type impurity doped in a sheet-shaped region, the δ doping area being formed on the n-type semiconductor layer; and a barrier layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the barrier layer being formed on the δ doping area.
摘要翻译：半导体器件包括：形成有半导体材料的电子转移层，电子转移层形成在半导体衬底上; 形成有比电子转移层宽的带隙的半导体材料的n型半导体层，n型半导体层形成在电子转移层上; 具有掺杂在片状区域中的n型杂质的δ掺杂区域，所述δ掺杂区域形成在所述n型半导体层上; 以及阻挡层，其形成有具有比电子转移层更宽的带隙的半导体材料，所述势垒层形成在δ掺杂区域上。

29. 发明申请

US20140299838A1 TRANSISTORS, METHODS OF FORMING TRANSISTORS AND DISPLAY DEVICES HAVING TRANSISTORS 有权
标题翻译：晶体管，形成晶体管的方法和具有晶体管的显示器件
公开(公告)号：US20140299838A1
公开(公告)日：2014-10-09
申请号：US14206071
申请日：2014-03-12
申请人： Samsung Display Co., Ltd.
发明人： Jin-Woo LEE , Moo-Jin KIM
IPC分类号： H01L29/786 , H01L29/165 , H01L29/267 , H01L29/66
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02422 , H01L21/0245 , H01L21/02513 , H01L21/02527 , H01L21/02532 , H01L21/02592 , H01L21/02675 , H01L21/02691 , H01L21/465 , H01L27/3262 , H01L29/04 , H01L29/1054 , H01L29/1606 , H01L29/165 , H01L29/267 , H01L29/42356 , H01L29/66045 , H01L29/66431 , H01L29/66742 , H01L29/66757 , H01L29/66969 , H01L29/7781 , H01L29/7782 , H01L29/78684 , H01L29/7869
摘要： A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.
摘要翻译：晶体管，显示器件和相关方法，所述晶体管包括衬底; 设置在所述衬底上的有源层图案，所述有源层图案包括硅和石墨烯; 设置在有源层图案上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 覆盖有源层图案和栅电极的绝缘夹层; 以及与有源层图案接触的源电极和漏电极。

30. 发明申请

US20140264459A1 High Mobility Transport Layer Structures for Rhombohedral Si/Ge/SiGe Devices 有权
标题翻译： Rhombohedral Si / Ge / SiGe器件的高迁移率传输层结构
公开(公告)号：US20140264459A1
公开(公告)日：2014-09-18
申请号：US14202699
申请日：2014-03-10
申请人： U.S.A. as represented by the National Aeronautics and Space Administration
发明人： Sang Hyouk Choi , Yeonjoon Park , Glen C. King , Hyun-Jung Kim , Kunik Lee
IPC分类号： H01L29/04 , H01L29/165 , H01L21/02
CPC分类号： H01L29/157 , H01L21/0242 , H01L21/02433 , H01L21/0245 , H01L21/02516 , H01L21/02532 , H01L21/02584 , H01L29/045 , H01L29/155 , H01L29/165 , H01L29/7782 , H01L31/0336 , H01L31/035236 , H01L31/03682 , H01L35/22 , Y02E10/546
摘要： An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhomhohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions.
摘要翻译：电子器件包括限定（0001）C面的三角晶体衬底。衬底可以包括蓝宝石或其他合适的材料。在晶体衬底的（0001）C面上设置多个矩阵取向的SiGe（111）取向晶体。第一材料区域设置在菱形排列的SiGe层上。第一区域包括本征或掺杂的Si，Ge或SiGe层。第一区域可以在包括n +掺杂SiGe或n +掺杂Ge的两个次级区域之间分层，由此第一区域从两个次级区域收集电子。

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