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21. 发明申请

US20140042447A1 METHOD AND SYSTEM FOR GALLIUM NITRIDE ELECTRONIC DEVICES USING ENGINEERED SUBSTRATES 有权
标题翻译：使用工程衬底的氮化镓电子器件的方法和系统
公开(公告)号：US20140042447A1
公开(公告)日：2014-02-13
申请号：US13572408
申请日：2012-08-10
申请人： Hui Nie , Donald R. Disney , Isik C. Kizilyalli
发明人： Hui Nie , Donald R. Disney , Isik C. Kizilyalli
IPC分类号： H01L29/80 , H01L29/20 , H01L21/20
CPC分类号： H01L21/0254 , H01L21/02645 , H01L21/6835 , H01L24/83 , H01L29/2003 , H01L29/66204 , H01L29/66212 , H01L29/66356 , H01L29/66446 , H01L29/739 , H01L29/8083 , H01L29/861 , H01L29/872 , H01L2221/68327 , H01L2224/04026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/32245 , H01L2224/83801 , H01L2224/8384 , H01L2924/12032 , H01L2924/13062 , H01L2924/00014 , H01L2924/00
摘要： A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.
摘要翻译：一种制造电子器件的方法包括提供包括III族氮化物种子层的工程化衬底结构，形成与III族氮化物种子层耦合的GaN基功能层，以及形成电耦合到至少一部分 GaN基功能层。该方法还包括将与GaN基功能层相对的载体衬底接合并去除工程衬底结构的至少一部分。该方法还包括形成电耦合到GaN基功能层的至少另一部分并去除载体衬底的第二电极结构。

22. 发明授权

US08524601B2 Method of manufacturing semiconductor device using Resolution Enhanced Lithography Assisted Chemical Shrinkage (RELACS) 有权
标题翻译：使用分辨率增强光刻辅助化学收缩制造半导体器件的方法（RELACS）
公开(公告)号：US08524601B2
公开(公告)日：2013-09-03
申请号：US13334213
申请日：2011-12-22
申请人： Kenichiro Kurahashi , Hidetoshi Koyama , Kazuyuki Onoe
发明人： Kenichiro Kurahashi , Hidetoshi Koyama , Kazuyuki Onoe
IPC分类号： H01L21/302
CPC分类号： H01L21/28264 , H01L29/2003 , H01L29/42316 , H01L29/66446 , H01L29/7787
摘要： A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off.
摘要翻译：一种制造半导体器件的方法包括在半导体层的表面上形成绝缘膜，在绝缘膜的表面上形成抗蚀剂，所述抗蚀剂具有开口，通过附着在所述抗蚀剂的内周上形成硬化层图案收缩剂到抗蚀剂，图案收缩剂与抗蚀剂进行交联反应，使用抗蚀剂和硬化层作为掩模蚀刻绝缘膜，去除硬化层，以及在表面上形成金属层半导体层，在绝缘膜的表面上和抗蚀剂的表面上。该方法还包括通过剥离去除抗蚀剂和抗蚀剂表面上金属层的部分。

23. 发明申请

US20130040431A1 InP-Based Transistor Fabrication 有权
公开(公告)号：US20130040431A1
公开(公告)日：2013-02-14
申请号：US13654531
申请日：2012-10-18
申请人： Taiwan Semiconductor Manufacturing Company
发明人： Peide Ye , Zhiyuan Cheng , Yi Xuan , Yanqing Wu , Bunmi Adekore , James Fiorenza
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L29/66522 , H01L21/02299 , H01L21/02301 , H01L21/02392 , H01L21/28264 , H01L29/517 , H01L29/66446 , H01L29/66462 , H01L29/778
摘要： Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

24. 发明申请

US20130032811A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN GATE 有权
标题翻译：用于使用注射门的GAN垂直JFET的方法和系统
公开(公告)号：US20130032811A1
公开(公告)日：2013-02-07
申请号：US13198655
申请日：2011-08-04
申请人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L29/808 , H01L29/20 , H01L21/337
CPC分类号： H01L29/8083 , H01L29/1066 , H01L29/1095 , H01L29/2003 , H01L29/66446 , H01L29/66909 , H01L29/66924
摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
摘要翻译：垂直III族氮化物场效应晶体管包括：包含第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点;以及漂移区域，包括耦合到漏极并邻近漏极设置的第二III族氮化物材料垂直方向场效应晶体管还包括沟道区，该沟道区包括耦合到漂移区的第三III族氮化物材料，至少部分围绕沟道区的栅极区和电耦合到栅极区的栅极接触。场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物场效应晶体管的工作期间的电流沿垂直方向。

25. 发明申请

US20110220967A1 PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS 审中-公开
公开(公告)号：US20110220967A1
公开(公告)日：2011-09-15
申请号：US13114460
申请日：2011-05-24
申请人： Gerard J. Sullivan , Amal Ikhlassi , Joshua I. Bergman , Berinder Brar , Gabor Nagy
发明人： Gerard J. Sullivan , Amal Ikhlassi , Joshua I. Bergman , Berinder Brar , Gabor Nagy
IPC分类号： H01L29/205 , H01L21/20
CPC分类号： H01L29/205 , H01L21/02463 , H01L21/02549 , H01L21/02631 , H01L29/66446
摘要： A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.

26. 发明授权

US07960782B2 Nitride semiconductor device and method for producing nitride semiconductor device 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US07960782B2
公开(公告)日：2011-06-14
申请号：US12342854
申请日：2008-12-23
申请人： Hirotaka Otake
发明人： Hirotaka Otake
IPC分类号： H01L29/66
CPC分类号： H01L29/2003 , H01L21/28264 , H01L29/4236 , H01L29/66446 , H01L29/7827
摘要： A nitride semiconductor device includes: a nitride semiconductor structure portion including a first layer made of an n-type group III nitride semiconductor, a second layer made of a group III nitride semiconductor containing a p-type impurity provided on the first layer and an n-type region formed on a part of the second layer, and having a wall surface extending over the first layer, a body region of the second layer other than the n-type region and the n-type region; a gate insulating film formed such that the gate insulating film is opposed to the body region on the wall surface; a gate electrode formed such that the gate electrode is opposed to the body region through the gate insulating film; a source electrode formed such that the source electrode is electrically connected to the n-type region; a drain electrode formed such that the drain electrode is electrically connected to the first layer; and a body electrode formed such that the body electrode is electrically connected to the body region.
摘要翻译：氮化物半导体器件包括：氮化物半导体结构部分，包括由n型III族氮化物半导体制成的第一层，由包含设置在第一层上的p型杂质的III族氮化物半导体制成的第二层和n 型区域形成在第二层的一部分上，并且具有在第一层上延伸的壁表面，除了n型区域和n型区域之外的第二层的主体区域; 栅极绝缘膜，其形成为使得栅极绝缘膜与壁表面上的体区相对; 形成为使得栅电极通过栅极绝缘膜与体区相对的栅电极; 源极电极，其形成为使得所述源极电极与所述n型区域电连接; 漏极，其形成为使得所述漏极电连接到所述第一层; 以及主体电极，其形成为使得主体电极与身体区域电连接。

27. 发明申请

US20090042344A1 InP-Based Transistor Fabrication 有权
标题翻译：基于InP的晶体管制造
公开(公告)号：US20090042344A1
公开(公告)日：2009-02-12
申请号：US12139010
申请日：2008-06-13
申请人： Peide Ye , Zhiyuan Cheng , Yi Xuan , Yanqing Wu , Bunmi Adekore , James Fiorenza
发明人： Peide Ye , Zhiyuan Cheng , Yi Xuan , Yanqing Wu , Bunmi Adekore , James Fiorenza
IPC分类号： H01L21/335 , H01L21/336
CPC分类号： H01L29/66522 , H01L21/02299 , H01L21/02301 , H01L21/02392 , H01L21/28264 , H01L29/517 , H01L29/66446 , H01L29/66462 , H01L29/778
摘要： Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
摘要翻译：形成包括基于InP的材料的结构的方法，例如用作反型的晶体管，增强型器件。可以通过ALD在包括In和P的半导体层上沉积电介质层。沟道层可以形成在具有类似于InP的晶格常数的晶格常数的缓冲层之上，缓冲层形成在具有晶格的衬底上常数与InP的晶格常数不同。

28. 发明授权

US11955527B2 Nano transistors with source/drain having side contacts to 2-D material 有权
公开(公告)号：US11955527B2
公开(公告)日：2024-04-09
申请号：US17351622
申请日：2021-06-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chao-Ching Cheng , Yi-Tse Hung , Hung-Li Chiang , Tzu-Chiang Chen , Lain-Jong Li , Jin Cai
IPC分类号： H01L29/00 , H01L29/06 , H01L29/20 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0665 , H01L29/2003 , H01L29/66446 , H01L29/66545 , H01L29/78696
摘要： A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

29. 发明公开

US20230317804A1 SEMICONDUCTOR DEVICE HAVING A LATERAL TRANSISTOR DEVICE AND AN INVERTER THAT INCLUDES THE SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20230317804A1
公开(公告)日：2023-10-05
申请号：US18326416
申请日：2023-05-31
申请人： Infineon Technologies Austria AG
发明人： Oliver Häberlen , Eric G. Persson , Reenu Garg
IPC分类号： H01L29/417 , H01L23/64 , H01L29/423 , H01L29/66 , H03K17/687
CPC分类号： H01L29/41758 , H01L23/642 , H01L29/42316 , H01L29/66446 , H03K17/6871 , H03K2217/0081
摘要： In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

30. 发明申请

US20190189748A1 LONG CHANNELS FOR TRANSISTORS 有权
公开(公告)号：US20190189748A1
公开(公告)日：2019-06-20
申请号：US15844923
申请日：2017-12-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： ROBIN HSIN KUO CHAO , CHOONGHYUN LEE , HENG WU , CHUN WING YEUNG , JINGYUN Zhang
IPC分类号： H01L29/10 , H01L21/8234 , H01L29/66 , H01L21/285 , H01L29/78 , H01L21/306
CPC分类号： H01L29/1037 , H01L21/28575 , H01L21/30604 , H01L21/823431 , H01L29/66446 , H01L29/66545 , H01L29/6656 , H01L29/66666 , H01L29/66795 , H01L29/7827 , H01L29/7851
摘要： A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.

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