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21. 发明申请

US20170136582A1 COMPOSITE SOLDER BALL, SEMICONDUCTOR PACKAGE USING THE SAME, SEMICONDUCTOR DEVICE USING THE SAME AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20170136582A1
公开(公告)日：2017-05-18
申请号：US15420140
申请日：2017-01-31
申请人： MEDIATEK Inc.
发明人： Tao Cheng , Wen-Sung Hsu , Shih-Chin Lin
IPC分类号： B23K35/02 , H01L25/10 , B23K35/26 , H01L23/498
CPC分类号： B23K35/0244 , B23K35/26 , B23K35/262 , B23K35/264 , B23K35/30 , B23K2101/40 , H01L23/49816 , H01L23/49833 , H01L23/49866 , H01L23/49894 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/105 , H01L2224/13014 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13561 , H01L2224/13582 , H01L2224/13611 , H01L2224/13639 , H01L2224/13647 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/014 , H01L2924/1434 , H01L2924/15331 , H01L2924/2076 , H01L2924/00
摘要： A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

22. 发明授权

US09613934B2 Interconnect structures with polymer core 有权
公开(公告)号：US09613934B2
公开(公告)日：2017-04-04
申请号：US14621936
申请日：2015-02-13
申请人： INTEL CORPORATION
发明人： Sandeep Razdan , Edward R. Prack , Sairam Agraharam , Robert L. Sankman , Shan Zhong , Robert M. Nickerson
IPC分类号： H01L25/065 , H01L23/00 , H01L25/10 , C09J9/02 , H01L23/498 , H01L21/56 , H01L23/528 , H01L23/532 , H01L25/00 , H01L23/31
CPC分类号： H01L25/0657 , C09J9/02 , H01L21/565 , H01L23/3128 , H01L23/49811 , H01L23/49866 , H01L23/528 , H01L23/53209 , H01L23/53228 , H01L23/53242 , H01L23/5329 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/95 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/12105 , H01L2224/13005 , H01L2224/13025 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/29078 , H01L2224/2929 , H01L2224/293 , H01L2224/2939 , H01L2224/29411 , H01L2224/29439 , H01L2224/29444 , H01L2224/29447 , H01L2224/29455 , H01L2224/29499 , H01L2224/73104 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2224/83191 , H01L2224/83851 , H01L2224/83856 , H01L2224/83862 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/12042 , H01L2924/15331 , H01L2924/181 , H01L2924/00014 , H01L2224/13611 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13613 , H01L2924/014 , H01L2924/207 , H01L2924/0665 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

23. 发明授权

US09601448B2 Electrode connection structure and electrode connection method 有权
公开(公告)号：US09601448B2
公开(公告)日：2017-03-21
申请号：US15094759
申请日：2016-04-08
申请人： Waseda University
发明人： Kohei Tatsumi
IPC分类号： H01L23/48 , H01L21/44 , H01L23/00 , H01L21/52 , H01L23/498
CPC分类号： H01L24/10 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/75 , H01L24/76 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/84 , H01L24/85 , H01L2224/0345 , H01L2224/03464 , H01L2224/04 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05173 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05673 , H01L2224/11334 , H01L2224/1134 , H01L2224/13012 , H01L2224/13017 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13294 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/13411 , H01L2224/136 , H01L2224/13611 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/24225 , H01L2224/24245 , H01L2224/245 , H01L2224/2499 , H01L2224/29012 , H01L2224/29017 , H01L2224/29147 , H01L2224/32227 , H01L2224/32245 , H01L2224/37147 , H01L2224/3716 , H01L2224/40095 , H01L2224/40227 , H01L2224/40991 , H01L2224/40996 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/48873 , H01L2224/48991 , H01L2224/48996 , H01L2224/73255 , H01L2224/73265 , H01L2224/73273 , H01L2224/73277 , H01L2224/75754 , H01L2224/76754 , H01L2224/81002 , H01L2224/81205 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81473 , H01L2224/81815 , H01L2224/8184 , H01L2224/81901 , H01L2224/8192 , H01L2224/82002 , H01L2224/82101 , H01L2224/82399 , H01L2224/83002 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/83464 , H01L2224/83473 , H01L2224/83815 , H01L2224/8384 , H01L2224/83901 , H01L2224/8392 , H01L2224/8492 , H01L2224/85205 , H01L2224/85447 , H01L2224/8592 , H01L2224/9201 , H01L2924/00011 , H01L2924/3656 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01028 , H01L2924/01074 , H01L2924/01023 , H01L2924/014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/01046 , H01L2924/01045 , H01L2224/18 , H01L2224/24 , H01L2224/82 , H01L2224/83205
摘要： An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

24. 发明授权

US09597752B2 Composite solder ball, semiconductor package using the same, semiconductor device using the same and manufacturing method thereof 有权
公开(公告)号：US09597752B2
公开(公告)日：2017-03-21
申请号：US14918698
申请日：2015-10-21
申请人： MEDIATEK Inc.
发明人： Tao Cheng , Wen-Sung Hsu , Shih-Chin Lin
IPC分类号： H01L23/48 , B23K35/02 , H01L23/00 , B23K35/26 , B23K35/30 , H01L23/498
CPC分类号： B23K35/0244 , B23K35/26 , B23K35/262 , B23K35/264 , B23K35/30 , B23K2101/40 , H01L23/49816 , H01L23/49833 , H01L23/49866 , H01L23/49894 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/105 , H01L2224/13014 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13561 , H01L2224/13582 , H01L2224/13611 , H01L2224/13639 , H01L2224/13647 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/014 , H01L2924/1434 , H01L2924/15331 , H01L2924/2076 , H01L2924/00
摘要： A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

25. 发明申请

US20160368104A1 Lead-Free Solder Alloy, Solder Material and Joined Structure 有权
标题翻译：无铅焊料，焊料和焊接结构
公开(公告)号：US20160368104A1
公开(公告)日：2016-12-22
申请号：US15120937
申请日：2015-02-19
申请人： KOKI COMPANY LIMITED
发明人： Atsushi Irisawa , Rie Wada
IPC分类号： B23K35/26 , H01L23/00 , B23K35/36
CPC分类号： B23K35/262 , B23K35/0222 , B23K35/26 , B23K35/36 , B23K2101/40 , C22C13/02 , H01L24/16 , H01L2224/13611 , H01L2224/1362 , H01L2224/13639 , H01L2224/13647 , H01L2224/13655 , H01L2224/13657 , H01L2924/01032 , H01L2924/014 , H05K3/3463
摘要： Provided are a lead-free solder alloy which consists of Sb in an amount of more than 3.0% but 10% or less by mass, and the balance including Sn, and others.
摘要翻译：本发明提供一种无铅焊料合金，其含量大于3.0％但为10质量％以下，余量为Sn等。

26. 发明申请

US20160358875A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160358875A1
公开(公告)日：2016-12-08
申请号：US15239745
申请日：2016-08-17
申请人： Advanced Semiconductor Engineering, Inc.
发明人： Yu-Hsiang HSIAO , Chiu-Wen LEE , Ping-Feng YANG , Kwang-Lung LIN
IPC分类号： H01L23/00 , H01L25/00 , C22C9/02 , B23K35/26 , B23K1/00 , C22C13/00 , H01L25/065 , B23K35/30
CPC分类号： H01L24/13 , B23K1/0016 , B23K35/262 , B23K35/302 , B23K2101/40 , C22C9/02 , C22C13/00 , H01L24/05 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/1182 , H01L2224/13025 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13686 , H01L2224/16146 , H01L2224/16503 , H01L2224/16507 , H01L2224/81193 , H01L2224/8181 , H01L2224/81815 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06582 , H01L2924/01029 , H01L2924/01327 , H01L2924/014 , H01L2924/181 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.
摘要翻译：半导体器件包括第一电路层，邻近第一电路层设置的铜柱，第二电路层和焊料层。第二电路层包括电接触和设置在电接触上的表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。焊料层设置在铜柱和表面光洁剂层之间。焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的两种或更多种的组合，第二IMC包括金和锡的组合，钯的组合和锡，或两者。

27. 发明申请

US20160351520A1 COPPER STRUCTURES WITH INTERMETALLIC COATING FOR INTEGRATED CIRCUIT CHIPS 有权
标题翻译：具有集成电路芯片的铜箔结构的铜结构
公开(公告)号：US20160351520A1
公开(公告)日：2016-12-01
申请号：US14944054
申请日：2015-11-17
申请人： Monolithic Power Systems, Inc.
发明人： Hunt Hang JIANG
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03825 , H01L2224/03914 , H01L2224/0401 , H01L2224/05022 , H01L2224/05096 , H01L2224/05124 , H01L2224/05166 , H01L2224/05547 , H01L2224/05557 , H01L2224/05559 , H01L2224/05572 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11825 , H01L2224/11848 , H01L2224/11901 , H01L2224/13007 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/13611 , H01L2224/16245 , H01L2224/80801 , H01L2224/80815 , H01L2924/01013 , H01L2924/01029 , H01L2924/0105 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/01047
摘要： An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.
摘要翻译：集成电路（IC）芯片包括在表面上具有金属间涂层的铜结构。 IC芯片包括具有集成电路的基板。金属焊盘电连接到集成电路。铜结构电连接到金属垫。焊料凸块设置在铜结构上。铜结构的表面具有金属间化合物的涂层。铜结构可以是再分布层和布置在再分布层上的铜柱。

28. 发明申请

US20160343692A1 Semiconductor Packaging Structure and Method 审中-公开
公开(公告)号：US20160343692A1
公开(公告)日：2016-11-24
申请号：US15230921
申请日：2016-08-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chun-Cheng Lin , Chung-Shi Liu , Kuei-Wei Huang , Cheng-Ting Chen , Wei-Hung Lin , Ming-Da Cheng
IPC分类号： H01L25/065 , H01L23/498 , H01L21/56 , H01L21/48 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/0273 , H01L21/486 , H01L21/56 , H01L21/76898 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/0231 , H01L2224/0239 , H01L2224/03452 , H01L2224/0401 , H01L2224/05083 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/1131 , H01L2224/11424 , H01L2224/1152 , H01L2224/1162 , H01L2224/11825 , H01L2224/11849 , H01L2224/13024 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13611 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01048 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/12042 , H01L2924/15311 , H01L2924/15321 , H01L2924/15747 , H01L2924/18161 , H01L2924/2064 , H01L2924/20641 , H01L2924/20642 , H01L2924/00014 , H01L2924/00
摘要： A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

29. 发明授权

US09449913B2 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias 有权
标题翻译： 3D互连结构包括与通过硅通孔组合的细间距单镶嵌背面金属再分配线
公开(公告)号：US09449913B2
公开(公告)日：2016-09-20
申请号：US13994668
申请日：2011-10-28
申请人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
发明人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
IPC分类号： H01L23/48 , H01L23/522 , H01L21/768 , H01L23/29 , H01L23/00
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76898 , H01L23/291 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/05624 , H01L2224/05647 , H01L2224/06131 , H01L2224/06181 , H01L2224/11334 , H01L2224/1146 , H01L2224/11823 , H01L2224/11825 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/13583 , H01L2224/13611 , H01L2224/13644 , H01L2224/13655 , H01L2224/13657 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/94 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2224/03 , H01L2224/11 , H01L2924/0105 , H01L2924/01015 , H01L2924/01074 , H01L2924/01079 , H01L2924/01047 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
摘要翻译：描述了三维互连结构和制造方法，其中金属再分配层（RDL）与硅通孔（TSV）集成并且使用单个镶嵌型工艺流程。氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

30. 发明授权

US09425164B1 Low alpha tin 有权
标题翻译：低阿尔法锡
公开(公告)号：US09425164B1
公开(公告)日：2016-08-23
申请号：US14950852
申请日：2015-11-24
申请人： International Business Machines Corporation
发明人： Charles L. Arvin , Michael S. Gordon
IPC分类号： H01L21/44 , H01L23/00 , H01L21/477
CPC分类号： H01L24/81 , H01L21/477 , H01L24/11 , H01L24/14 , H01L2224/13611 , H01L2224/81024 , H01L2224/81055
摘要： A non alpha controlled Tin including Tin and a trace amount of Polonium may be converted to a low alpha emission Tin by concentrating and removing at least some of the Polonium. The non alpha controlled Tin may be a raw material or a solder bump upon a semiconductor wafer, chip, or carrier. The Polonium may be concentrated by oxidizing an exterior portion of the non alpha controlled Tin. If the non alpha controlled Tin is a raw material, the oxidized exterior portion of the non alpha controlled Tin may be stripped. If the non alpha controlled Tin is a solder bump, the oxidized exterior portion of the solder bump may be removed by applying flux to the solder bump, reflowing the solder bump to dissolve the oxidized exterior portion and the concentrated Po into the flux, and cleaning the flux from the solder bump.
摘要翻译：包括锡和痕量的onium的非α控制锡可以通过浓缩和去除至少一些Pol藜来转化为低α发射锡。非α控制锡可以是半导体晶片，芯片或载体上的原料或焊料凸块。可以通过氧化非α受控锡的外部部分来浓缩onium。如果非α受控锡是原料，则非α受控锡的氧化外部部分可能被剥离。如果非α控制的锡是焊料凸点，则可以通过向焊料凸块施加焊剂来去除焊料凸起的氧化外部部分，回流焊料凸块以将氧化的外部部分和浓缩的Po溶解到焊剂中，并且清洁来自焊料凸块的焊剂。

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