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21. 发明授权

US08964473B2 Select gate materials having different work functions in non-volatile memory 有权
标题翻译：选择在非易失性存储器中具有不同功能的栅极材料
公开(公告)号：US08964473B2
公开(公告)日：2015-02-24
申请号：US14047764
申请日：2013-10-07
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Masaaki Higashitani
IPC分类号： G11C16/04 , G11C16/12 , G11C11/56 , G11C16/10 , G11C16/34 , H01L29/49 , H01L27/115
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0475 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/4983
摘要： In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different work functions in their control gates so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a higher work function so that the channel potential under it is lower, and the next SGD transistor has a lower work function so that the channel potential under it is higher. The different work functions can be provided by using different control gate materials for the SGD transistors. One option uses p+ polysilicon and n+ polysilicon to provide higher and lower work functions, respectively. Metal or metal silicide can also be used. A single SGD transistor with different control gate materials could also be used.
摘要翻译：在3D堆叠的非易失性存储器件中，多个更小的漏极端选择栅极（SGD）晶体管代替一个较大的SGD晶体管。 SGD晶体管在其控制栅极中具有不同的功函数，使得在编程操作期间，在禁止的NAND串中产生不连续的沟道电位。最靠近位线的SGD晶体管具有更高的功函数，使得其下的沟道电位较低，下一个SGD晶体管具有较低的功函数，使得其下的沟道电位较高。可以通过使用SGD晶体管的不同控制栅极材料来提供不同的功能。一种选择是使用p +多晶硅和n +多晶硅分别提供更高和更低的功函数。也可以使用金属或金属硅化物。也可以使用具有不同控制栅极材料的单个SGD晶体管。

22. 发明授权

US08923052B2 Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating 有权
标题翻译：具有易失性和多位，非易失性功能和操作方法的半导体存储器
公开(公告)号：US08923052B2
公开(公告)日：2014-12-30
申请号：US13196471
申请日：2011-08-02
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C11/34 , G11C14/00 , H01L27/105 , H01L27/108 , H01L29/78 , H01L27/115 , G11C16/04
CPC分类号： G11C14/0018 , G11C11/5671 , G11C14/00 , G11C16/02 , G11C16/0466 , G11C16/0475 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/115 , H01L29/7841 , H01L29/792
摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.
摘要翻译：描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 包括第一和第二存储位置的捕获层被配置为将数据彼此独立地存储为非易失性存储器，以及位于捕获层上方的控制栅极。

23. 发明授权

US08917549B2 NOR flash memory array structure, mixed nonvolatile flash memory and memory system comprising the same 有权
标题翻译： NOR闪存阵列结构，混合非易失性闪存和包含其的存储系统
公开(公告)号：US08917549B2
公开(公告)日：2014-12-23
申请号：US13806314
申请日：2012-11-30
申请人： Tsinghua University
发明人： Liyang Pan , Lifang Liu
IPC分类号： G11C16/04 , H01L21/28 , H01L29/10 , H01L27/115 , H01L29/792 , G11C11/56
CPC分类号： G11C16/0466 , G11C11/5621 , G11C16/0475 , G11C16/0483 , H01L21/28282 , H01L27/11563 , H01L29/1041 , H01L29/7923
摘要： A NOR flash memory array structure is provided, comprising: a substrate (100); and a two dimensional memory array structure formed on the substrate (100) and comprising: a plurality of memory cell columns arranged in a first direction, and each memory cell column including a plurality of memory cells (300), in which each memory cell (300) comprises: a channel region (308) located on the substrate (100), a gate structure located on the channel region (308) and formed by a tunneling oxide layer (304), a silicon nitride layer (303), a barrier oxide layer (302) and a polysilicon gate layer (301) stacked sequentially, a source region (306) and a drain region (305) located at a first edge and a second edge of the gate structure respectively; a plurality of word lines WL; a source line SL for connecting the source regions of all the memory cells; and a plurality of bit lines BL.
摘要翻译：提供NOR闪存阵列结构，包括：衬底（100）; 以及形成在所述基板（100）上的二维存储器阵列结构，并且包括：沿第一方向布置的多个存储单元列，并且每个存储单元列包括多个存储单元（300），其中每个存储器单元 300）包括：位于所述衬底（100）上的沟道区（308），位于所述沟道区（308）上并由隧道氧化物层（304）形成的栅极结构，氮化硅层（303），栅极氧化物层（302）和多晶硅栅极层（301），分别位于栅极结构的第一边缘和第二边缘处的源极区（306）和漏极区（305）多个字线WL; 用于连接所有存储单元的源极区域的源极线SL; 和多个位线BL。

24. 发明授权

US08854902B2 Write self timing circuitry for self-timed memory 有权
标题翻译：为自定时存储器写自定时电路
公开(公告)号：US08854902B2
公开(公告)日：2014-10-07
申请号：US13474825
申请日：2012-05-18
申请人： Nishu Kohli
发明人： Nishu Kohli
IPC分类号： G11C7/00 , G11C11/56 , G11C16/04 , G11C11/413
CPC分类号： G11C11/5621 , G11C7/227 , G11C11/413 , G11C11/419 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0475
摘要： A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.
摘要翻译：自定时存储器包括多个写入定时器单元。参考写入驱动器电路将逻辑低电平写入写入定时器单元的真实侧。每个写入定时器单元包括其栅极耦合到内部真实节点的上拉晶体管。通过检测在写定时器单元的补码侧的逻辑值写入的完成并响应于检测到的完成而发信号通知自拍定时器存储器的复位来实现自定时。为了更好地调整写入定时器单元中的写入完成与存储器中写入的实际完成，通过在连接的内部真实节点处增加较低的逻辑电平电平来降低写入定时器单元上拉晶体管的栅极到源极电压通过驱动电路操作将低逻辑状态写入写定时器单元的真实面。

25. 发明申请

US20140293701A1 Adjusting Control Gate Overdrive Of Select Gate Transistors During Programming Of Non-Volatile Memory 有权
标题翻译：在非易失性存储器编程期间调整选择栅极晶体管的控制栅极过驱动
公开(公告)号：US20140293701A1
公开(公告)日：2014-10-02
申请号：US14047381
申请日：2013-10-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yingda Dong , Masaaki Higashitani
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0475 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/4983
摘要： In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided.
摘要翻译：在3D堆叠的非易失性存储器件中，多个更小的漏极端选择栅极（SGD）晶体管代替一个较大的SGD晶体管。 SGD晶体管具有不同的控制栅极过驱动电压，使得在编程操作期间，在禁止的NAND串中产生不连续的沟道电位。最靠近位线的SGD晶体管具有较低的控制栅极过驱动电压，使得其下的沟道电位较低，并且下一个SGD晶体管具有较高的控制栅极过驱动电压，使得其下的沟道电位较高。可以通过编程不同的阈值电压或通过为SGD晶体管提供不同的控制栅极电压来提供不同的控制栅极过驱动电压。可以避免由于漏极引起的屏障降低导致的Vsgd窗口的不期望的减少。

26. 发明申请

US20140241067A1 METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY 有权
标题翻译：通过引用从闪存中读取的位序列的二进制数字分配特性来读取存储在闪存中的数据的方法和装置
公开(公告)号：US20140241067A1
公开(公告)日：2014-08-28
申请号：US14277007
申请日：2014-05-13
申请人： Silicon Motion Inc.
发明人： Tsung-Chieh Yang
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/0475 , G11C16/0483 , G11C16/3427 , G11C29/52 , G11C2211/5644 , G11C2211/5648 , H03M13/152
摘要： A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
摘要翻译：用于读取存储在闪速存储器中的数据的方法至少包括以下步骤：控制闪速存储器对包括在闪速存储器中的多个存储器单元执行多个读取操作; 分别从存储单元获取多个位序列，其中读操作通过利用不同的控制栅极电压设置从存储单元读取预定位序的位; 以及根据比特序列的二进制数字分配特性来确定存储器单元的读出信息。

27. 发明申请

US20140192594A1 P-CHANNEL 3D MEMORY ARRAY 有权
公开(公告)号：US20140192594A1
公开(公告)日：2014-07-10
申请号：US14019183
申请日：2013-09-05
申请人： Macronix International Co., Ltd.
发明人： Hang-Ting Lue
IPC分类号： G11C16/10
CPC分类号： G11C16/0475 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C2213/71 , H01L27/1157 , H01L27/11578
摘要： A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce −FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce −FN hole tunneling in selected blocks of cells.
摘要翻译：包括3D NAND阵列的p通道闪速存储器件具有优异的性能特性。用于操作3D，p通道NAND阵列的技术包括选择性编程，选择性（位）擦除和块擦除。选择性编程偏置布置引起带对隧道电流热电子注入，以增加所选单元格中的阈值电压。选择性擦除偏置布置引起-FN空穴隧道以降低选定单元中的阈值电压。此外，块擦除偏置布置在选定的单元块中引起-FN空穴隧穿。

28. 发明申请

US20140065776A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140065776A1
公开(公告)日：2014-03-06
申请号：US13964576
申请日：2013-08-12
申请人： Renesas Electronics Corporation
发明人： Tatsuyoshi MIHARA
IPC分类号： H01L29/66
CPC分类号： H01L27/0629 , G11C11/5671 , G11C16/0466 , G11C16/0475 , H01L21/823468 , H01L27/1104 , H01L27/11565 , H01L27/11568 , H01L29/4234 , H01L29/66545 , H01L29/66833 , H01L29/792
摘要： The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.
摘要翻译：实现具有分割门型MONOS存储器的半导体器件的可靠性的提高。依次形成ONO膜和第二多晶硅膜，以填充第一多晶硅膜和虚拟栅电极。然后，去除虚拟栅电极。然后，对第一多晶硅膜和第二多晶硅膜的顶表面进行抛光，从而在由第一多晶硅膜经由ONO膜形成的控制栅电极的侧壁处形成由第二多晶硅膜形成的存储栅电极。结果，形成了侧壁高度垂直的存储栅电极，膜厚度均匀。

29. 发明授权

US08462557B2 Methods of operating memory cell having asymmetric band-gap tunnel insulator using direct tunneling 有权
标题翻译：使用直接隧道操作具有非对称带隙隧道绝缘子的存储单元的方法
公开(公告)号：US08462557B2
公开(公告)日：2013-06-11
申请号：US12941458
申请日：2010-11-08
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/4232 , H01L29/42336 , H01L29/513 , H01L29/7881
摘要： Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.
摘要翻译：使用直接隧道操作具有非对称带隙隧道绝缘体的双栅极存储单元的方法。非对称带隙隧道绝缘子允许低电压直接隧道编程和有空和/或电子的有效擦除，同时保持高电荷阻挡屏障和深载流子捕获位点以获得良好的电荷保留。

30. 发明授权

US08456941B2 Table lookup voltage compensation for memory cells 有权
公开(公告)号：US08456941B2
公开(公告)日：2013-06-04
申请号：US13481582
申请日：2012-05-25
申请人： Boon-Aik Ang , Derric J. H. Lewis
发明人： Boon-Aik Ang , Derric J. H. Lewis
IPC分类号： G11C7/00
CPC分类号： G11C16/30 , G11C16/0458 , G11C16/0475
摘要： Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell.

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